Validation analysis and test flow optimization of VLSI chip

Yanzhuo Tan, Yinhe Han, Xiaowei Li, Feiyin Lu, Yuchuan Chen. Validation analysis and test flow optimization of VLSI chip. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 5666-5669, IEEE, 2005. [doi]

Abstract

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