Valentin Gies, Thierry M. Bernard, Alain Mérigot. Hardware reduction using a 6-connectivity interconnection network over a 4-connectivity VLSI asynchronous array processor. In International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan. pages 2227-2230, IEEE, 2005. [doi]
Abstract is missing.