Takeshi Sakata - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 13 from 13

2005

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookupSatoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara. icc 2005: 1048-1052 [doi]

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network routerSatoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara. jssc, 40(4):853-861, 2005. [doi]

1999

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line schemeHitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura. jssc, 34(8):1084-1090, 1999. [doi]

1997

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memoryHiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya. jssc, 32(5):655-661, 1997. [doi]

1995

1994

Subthreshold-current reduction circuits for multi-gigabit DRAM'sTakeshi Sakata, Kiyoo Itoh 0001, Masashi Horiguchi, Masakazu Aoki. jssc, 29(7):761-769, July 1994. [doi]

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM'sTakeshi Sakata, Kiyoo Itoh 0001, Masashi Horiguchi, Masakazu Aoki. jssc, 29(8):887-894, August 1994. [doi]

1993

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI'sMasashi Horiguchi, Takeshi Sakata, Kiyoo Itoh 0001. jssc, 28(11):1131-1135, November 1993. [doi]

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arraysTakayuki Kawahara, Takeshi Sakata, Kiyoo Itoh 0001, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki. jssc, 28(7):816-823, July 1993. [doi]

6 synapse neural networkTakao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito. tnn, 4(3):387-393, 1993. [doi]

1991

A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architectureKatsutaka Kimura, Takeshi Sakata, Kiyoo Itoh 0001, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto. jssc, 26(11):1511-1518, November 1991. [doi]

1985

A circuit comparison system for bipolar linear LSITakeshi Sakata, Aritoyo Kishimoto. dac 1985: 429-434 [doi]

Sign in or sign up to see more results.

runs on WebDSL