An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture

Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda. An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. J. Solid-State Circuits, 30(11):1165-1173, November 1995. [doi]

Abstract

Abstract is missing.