Anant Singh, Michael Ciraula, Don Weiss, John Wuu, Philippe Bauser, Paul de Champs, Hamid Daghighian, David Fisch, Philippe Graber, Michel Bron. A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology. In IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009. pages 460-461, IEEE, 2009. [doi]
Abstract is missing.