A 43.7mW 96GHz PLL in 65nm CMOS

Kun-Hung Tsai, Shen-Iuan Liu. A 43.7mW 96GHz PLL in 65nm CMOS. In IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009. pages 276-277, IEEE, 2009. [doi]

Abstract

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