A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS

M. Kumarasamy Raja, Dan Lei Yan, Aruna B. Ajjikuttira. A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS. In Doris Schmitt-Landsiedel, Tobias Noll, editors, 33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007. pages 524-527, IEEE, 2007. [doi]

Abstract

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