David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai. Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. In Doris Schmitt-Landsiedel, Tobias Noll, editors, 33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007. pages 190-193, IEEE, 2007. [doi]
Abstract is missing.