David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai. Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. In Doris Schmitt-Landsiedel, Tobias Noll, editors, 33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007. pages 190-193, IEEE, 2007. [doi]
@inproceedings{LevacqYKTS07,
title = {Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution},
author = {David Levacq and Muhammad Yazid and Hiroshi Kawaguchi and Makoto Takamiya and Takayasu Sakurai},
year = {2007},
doi = {10.1109/ESSCIRC.2007.4430277},
url = {https://doi.org/10.1109/ESSCIRC.2007.4430277},
researchr = {https://researchr.org/publication/LevacqYKTS07},
cites = {0},
citedby = {0},
pages = {190-193},
booktitle = {33rd European Solid-State Circuits Conference, ESSCIRC 2007, Munich, Germany, 11-13 September 2007},
editor = {Doris Schmitt-Landsiedel and Tobias Noll},
publisher = {IEEE},
isbn = {978-1-4244-1125-2},
}