Elizabeth J. Brauer - researchr alias

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Viewing Publication 1 - 19 from 19

2009

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDPArmin Tajalli, Elizabeth J. Brauer, Yusuf Leblebici. mj, 40(6):973-978, 2009. [doi]

2008

2007

Ultra low power subthreshold MOS current mode logic circuits using a novel load device conceptArmin Tajalli, Eric A. Vittoz, Yusuf Leblebici, Elizabeth J. Brauer. esscirc 2007: 304-307 [doi]

2006

Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML CellsStéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer. vlsi 2006: 234-238 [doi]

Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit designElizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici. iscas 2006: [doi]

2004

Finding efficient inductor geometries in digital CMOS process for RF applicationsElizabeth J. Brauer, Vikram Magoon. iastedCCS 2004: 558-561

Low noise MCML prefix adders using 0.18 µm CMOS technologyElizabeth J. Brauer, Yusuf Leblebici. iastedCCS 2004: 467-470

Sub-70 PS full adder IN 0.18 µm CMOS current-mode logicElizabeth J. Brauer, Yusuf Leblebici. iastedCCS 2004: 483-487

1999

Hardware implementation of a neural network pattern shaper algorithmElizabeth J. Brauer, James J. Abbas, Brian Callaway, Joshua Colvin, John Farris. ijcnn 1999: 2315-2318 [doi]

1998

Additive Decomposition Applied to the Semiconductor Drift-Diffusion ModelElizabeth J. Brauer, Marek Turowski, James M. McDonough. vlsi, 1998(1):393-399, 1998. [doi]

1997

Analog Circuit Model of Lamprey Unit Pattern GeneratorElizabeth J. Brauer, Ranu Jung, Denise M. Wilson, James J. Abbas. glvlsi 1997: 137-142 [doi]

A Full-Swing Bootstrapped BiCMOS BufferElizabeth J. Brauer, Pradeep Elamanchili. glvlsi 1997: 8-13 [doi]

Sensitivity analysis of an analog circuit model of lamprey unit pattern generatorElizabeth J. Brauer, Ranu Jung, Denise M. Wilson, James J. Abbas. icnn 1997: 975-979 [doi]

1995

An algorithm for functional verification of digital ECL circuitsElizabeth J. Brauer, Sung-Mo Kang. tcad, 14(12):1546-1556, 1995. [doi]

Estimating Node Voltages in Bipolar Circuits Using Linear ProgrammingElizabeth J. Brauer, Sung-Mo Kang. iscas 1995: 901-903

An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node EquationsElizabeth J. Brauer, Sung-Mo Kang. iscas 1995: 1580-1583

1993

Functional Verification of ECL Circuits Including Voltage RegulatorsElizabeth J. Brauer, Sung-Mo Kang. iscas 1993: 1710-1713

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