A fast analytical technique for estimating the bounds of on-chip clock wire inductance - researchr publication

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Yi-Chang Lu, Kaustav Banerjee, Mustafa Celik, Robert W. Dutton. A fast analytical technique for estimating the bounds of on-chip clock wire inductance. In Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, CICC 2001, San Diego, CA, USA, May 6-9, 2001. pages 241-244, IEEE, 2001. [doi]

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