Wei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel. Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability. In Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998. pages 519-522, IEEE, 1998. [doi]
Abstract is missing.