Bonnie Wang - researchr alias

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Viewing Publication 1 - 3 from 3

2005

A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interfaceJeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Philip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan. jssc, 40(9):1829-1838, 2005. [doi]

2004

A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interfaceJeffrey Tyhach, Bonnie Wang, Chiakang Sung, Joseph Huang, Khai Nguyen, Xiaobao Wang, Yan Chong, Phlip Pan, Henry Kim, Gopinath Rangan, Tzung-Chin Chang, Johnson Tan. cicc 2004: 431-434 [doi]

1998

A silicon efficient FLEX 6000 programmable logic architectureChiakang Sung, Richard Cliff, Joseph Huang, Bonnie Wang, Khai Nguyen, Xtaobao Wang, Kerry Veenstra, Bruce Pedersen, John Turner. cicc 1998: 273-276 [doi]

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