Gary Feierbach, Vijay Gupta. True Coverage: A Goal of Verification. In 4th International Symposium on Quality of Electronic Design (ISQED 2003), 24-26 March 2003, San Jose, CA, USA. pages 75-78, IEEE Computer Society, 2003. [doi]
This paper discusses the use of systematic stuck faults to test the coverage of a suite of tests. This methodology was found to be useful in developing full coverage and to create a short suite with high coverage for a quick test of changes made to the logic design.