Abstract is missing.
- Technology CAD: Technology Modeling, Device Design and SimulationSamar Saha, Bhaskar Gadepally. 3-5 [doi]
- Physical Design Trends and Layout-Based Fault ModelingSusmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah. 6-8 [doi]
- High Level Design Validation: Current Practices and Future DirectionsIndradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita. 9-11 [doi]
- System Software for Embedded ApplicationsKrithi Ramamritham, Kavi Arya, Gerhard Fohler. 12-14 [doi]
- Design Challenges in Sub-100nm High Performance MicroprocessorsSiva Narendra, Vasantha Erraguntla, James Tschanz, Nitin Borkar. 15-17 [doi]
- Bridging the Gap between Asynchronous Design and DesignersPeter A. Beerel, Jordi Cortadella, Alex Kondratyev. 18-20 [doi]
- Embedded Test for Low Cost ManufacturingJanusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht. 21-23 [doi]
- Synchronous Methodology for Designing Hardware, Software and Mixed Embedded SystemsGérard Berry. 24 [doi]
- High Speed Integrated A to D ConvertersP. Jespers. 29 [doi]
- CMOS Scaling for sub-90 nm to sub-10 nmHiroshi Iwai. 30 [doi]
- Techniques for very low-voltage operation of continuous-time analog CMOS circuitsJaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín. 39 [doi]
- Design of Amplifier with Rail-to-Rail CMR with 1V Power SupplySrinjoy Mitra, A. N. Chandorkar. 52-56 [doi]
- Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output SwingS. V. Gopalaiah, A. P. Shivaprasad, Sukanta K. Panigrahi. 57 [doi]
- Modeling and Estimation of Leakage in Sub-90nm DevicesArijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy. 65 [doi]
- Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAsMaitrali Marik, Ajit Pal. 73-78 [doi]
- Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAsD. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar. 79-84 [doi]
- Synthesis of Low Power High Performance Dual-VT PTL CircuitsDebasis Samanta, Ajit Pal. 85 [doi]
- Formal Verification of C Language Based VLSI DesignsMasahiro Fujita. 93 [doi]
- Formal Verification of Modules under Real Time Environment ConstraintsAnsuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti. 103-108 [doi]
- Property Refinement Techniques for Enhancing Coverage of Formal Property VerificationPrasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan. 109-114 [doi]
- Towards The Complete Elimination of Gate/Switch Level SimulationsNarayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham. 115 [doi]
- On Design and Implementation of an Embedded Automatic Speech Recognition SystemSujay Phadke, Rhishikesh Limaye, Siddharth Verma, Kavitha Subramanian. 127-132 [doi]
- Embedded Hardware Face DetectionTheo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf. 133 [doi]
- Algorithmic Macromodelling Methods for Mixed-Signal SystemsJaijeet S. Roychowdhury. 141 [doi]
- An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass /Delta/SigmaAD ModulatorsHao San, Haruo Kobayashi, Shinya Kawakami, Nobuyuki Kuroiwa. 151-156 [doi]
- Error Correction In Pipelined ADCS Using Arbitrary Radix CalibrationAnup Savla, Jennifer Leonard, Arun Ravindran. 157-162 [doi]
- A 2.5GHz CMOS Fully-Integrated /Delta/Sigma-Controlled Fractional-N Frequency SynthesizerRasoul Dehghani. 163-167 [doi]
- A Switch-Cap Regulator for SoC ApplicationsNitin Bansal, Amit Katyal. 168 [doi]
- Automated Architectural Optimization of Digital FIR FiltersRonald W. Mehler, Dian Zhou. 177-182 [doi]
- Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache DesignsRui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone. 183-188 [doi]
- Bridge Over Troubled Wrappers: Automated Interface SynthesisVijay D Silva, S. Ramesh, Arcot Sowmya. 189-194 [doi]
- Gate Sizing and Buffer Insertion using Economic Models for Power OptimizationAshok K. Murugavel, N. Ranganathan. 195-200 [doi]
- Charge-Sharing-Problem Reduced Split-Path Domino LogicSeok-Soo Yoon, Seok-Ryong Yoon, Seon Wook Kim, Chulwoo Kim. 201 [doi]
- Low Energy Switch Block For FPGAsRohini Krishnan, José Pineda de Gyvez. 209-214 [doi]
- Leakage Reduction techniques in a 0.13um SRAM CellSergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung. 215-221 [doi]
- Leakage-Proof Domino Circuit Design for Deep Sub-100nm TechnologiesGe Yang, Zhongda Wang, Sung-Mo Kang. 222-227 [doi]
- A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked TransistorsNarender Hanchate, Nagarajan Ranganathan. 228-233 [doi]
- Analysis and Optimization of Enhanced MTCMOS SchemeRahul M. Rao, Jeffrey L. Burns, Richard B. Brown. 234-239 [doi]
- Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational LogicKaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj. 240 [doi]
- New frontiers for embedded computingVictor Yodaiken. 249 [doi]
- An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC ArchitecturesKrishnan Srinivasan, Karam S. Chatha. 255-260 [doi]
- Energy-Optimizing Source Code Transformations for OS-driven Embedded SoftwareYunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 261-266 [doi]
- Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance OptimizationWeidong Wang, Anand Raghunathan, Niraj K. Jha. 267 [doi]
- Technological Challenges of Advanced CMOS Processing and Their Impact on Design AspectsCor Claeys. 275 [doi]
- Response Surface Modeling of 100nm CMOS Process Technology using Design of ExperimentH. C. Srinivasaiah, Navakanta Bhat. 285-290 [doi]
- Screening of Hot Electron Effect During Plasma ProcessingPurushothaman Srinivasan, B. Vootukuru, Durga Misra. 291 [doi]
- Designing Reconfigurable Systems in LavaSatnam Singh. 299-306 [doi]
- Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-ChipsKrishna Sekar, Kanishka Lahiri, Sujit Dey. 307 [doi]
- Assertion Based Verification Using HDVLKausik Datta, P. P. Das. 319 [doi]
- Design and Implementation of a Parallel Verilog Simulator: PVSimTun Li, Yang Guo, Sikun Li. 329-334 [doi]
- Energy Profiler for Hardware/Software Co-DesignRaghukiran Sreeramaneni, Sarma B. K. Vrudhula. 335 [doi]
- A Tuturial on the Emerging Nanotechnology DevicesTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell. 343-360 [doi]
- Design Considerations for Next Generation Wireless Power-Aware Microsensor NodesDavid D. Wentzloff, Benton H. Calhoun, Rex Min, Alice Wang, Nathan Ickes, Anantha Chandrakasan. 361 [doi]
- A Vision for the Broadband NetworkBill Witowsky. 373 [doi]
- A System Approach to Energy ManagementDennis Monticelli. 377 [doi]
- Design for Verification with SystemVerilogPhil Moorby. 378 [doi]
- A 800 MHz System-on-Chip for Wireless Infrastructure ApplicationsSanjive Agarwala, Paul Wiley, Arjun Rajagopal, Anthony M. Hill, Raguram Damodaran, Lewis Nardini, Tim Anderson, Steven Mullinnix, Jose Flores, Heping Yue, Abhijeet Chachad, John Apostol, Kyle Castille, Usha Narasimha, Tod Wolf, N. S. Nagaraj, Manjeri Krishnan, Luong Nguyen, Todd Kroeger, Mike Gill, Peter Groves, Bill Webster, Joel Graber, Christine Karlovich. 381 [doi]
- A Low Voltage, Low Noise CMOS RF Receiver Front-EndJie Long, Robert J. Weber. 393-397 [doi]
- Design of RF Tuner for Cable Modem ApplicationsV. Veeresh Babu, Sumantra Seth, A. N. Chandorkar. 398-403 [doi]
- Design and Implementation of 935 MHz FM Transceiver for Radio Telemetry and 2.45 GHz Direct AQPSK Transmitter in CMOSAmlan Ghosh, Bevin G. Perumana, Ashudeb Dutta, Padmanava Sen, Yogesh Kumar, Vipul Garg, T. K. Bhattacharyya, Nirmal B. Chakrabarti. 404-409 [doi]
- Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25 ?I m CMOSPadmanava Sen, Vipul Garg, Ramesh Garg, Nirmal B. Chakrabarti. 410-415 [doi]
- Design, Analysis, and Implementation of Analog Complex Filter for Low-IF Wireless LAN ApplicationT. Hui Teo, Ee-Sze Khoo, Dasgupta Uday, Chin-Boon Tear. 416 [doi]
- Interconnect Modeling for Copper/Low-k TechnologiesN. S. Nagaraj, Tom Bonifield, Abha Singh, Roger Griesmer, Poras T. Balsara. 425 [doi]
- Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive CouplingPuneet Gupta, Andrew B. Kahng. 431-436 [doi]
- Static Timing Analysis of Irreversible Crosstalk Noise Pulse FaultsMarong Phadoongsidhi, Kewal K. Saluja. 437-442 [doi]
- A Bus Encoding Technique for Power and Cross-talk MinimizationP. Subrahmanya, R. Manimegalai, V. Kamakoti, Madhu Mutyam. 443-448 [doi]
- Intra-Bus Crosstalk Estimation Using Word-Level StatisticsSuvodeep Gupta, Srinivas Katkoori. 449-454 [doi]
- On Buffering Schemes for Long Multi-Layer NetsVani Prasad, Madhav P. Desai. 455 [doi]
- On-chip testing of embedded transducersSalvador Mir, Libor Rufer, Bernard Courtois. 463 [doi]
- Defect Diagnosis Based on Pattern-Dependent Stuck-At FaultsIrith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Enamul Amyeen. 475-480 [doi]
- Untestable Fault Identification using Recurrence Relations and Impossible Value AssignmentsManan Syal, Michael S. Hsiao. 481-486 [doi]
- Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging FaultsHafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya. 487-492 [doi]
- Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test ModeJosh Yang, Baosheng Wang, André Ivanov. 493-498 [doi]
- Neural Network Model for Testing Stuck-at and Delay Faults in Digital CircuitPan Zhongliang. 499 [doi]
- Challenges in the Design of Embedded Real-time DSP SoCsMahesh Mehendale. 507-511 [doi]
- Multiprocessor Architectures for Embedded System-on-chip ApplicationsC. P. Ravikumar. 512-519 [doi]
- System-on-Chip (SoC): Clocking and Synchronization IssuesRamalingam Sridhar. 520 [doi]
- Package-silicon co-design - Experiment with an SOC designP. R. Suresh, P. K. Sundararajan, Anshuli Goel, H. Udayakumar, C. Srinivasan, Vasudev Sinari, Raghavendrakumar Ravinutala. 531 [doi]
- A tunable gm-C filter with low variation across Process, Voltage and TemperatureQadeer Ahmad Khan, Sanjay Kumar Wadhwa, Kulbhushan Misri. 539-544 [doi]
- The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performanceK. Narasimhulu, Siva Narendra, V. Ramgopal Rao. 545-550 [doi]
- A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon TunabilityS. S. Prasad, Pradip Mandal. 551 [doi]
- Evaluation of pausible clocking for interfacing high speed IP cores in GALS FrameworkJoycee Mekie, Supratik Chakraborty, Dinesh K. Sharma. 559-564 [doi]
- A Novel Technique Towards Eliminating the Global Clock in VLSI CircuitsG. Hazari, Madhav P. Desai, A. Gupta, S. Chakraborty. 565-570 [doi]
- A Distributed and Pipelined Controller for a Modular and Scalable Hardware EmulatorAditya Mittal, Madhav P. Desai. 571 [doi]
- Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based ApproachJens Bieger, Sorin A. Huss, Michael Jung, Stephan Klaus, Thomas Steininger. 577 [doi]
- Can SAT be used to Improve Sequential ATPG Methods?Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain. 585 [doi]
- Program Slicing for ATPG-Based Property CheckingVivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham. 591-596 [doi]
- Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing FailuresAman Kokrady, C. P. Ravikumar. 597 [doi]
- Tamper Resistance Mechanisms for Secure, Embedded SystemsSrivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar. 605 [doi]
- A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency SynthesisR. Dehghani, Seyed Mojtaba Atarodi, B. Bornoosh, Ali Afzali-Kusha. 615-618 [doi]
- A New Approach To Topology Selection For Cell-Level Analog CircuitsS. Nagar, Baquer Mazhari. 619-622 [doi]
- Quantitative Model for Thermal Behaviour of an Analog Integrated CircuitGagandeep S. Sandha, Pawan K. Singh, C. Pradeep Kumar, D. Nagchoudhuri. 623-626 [doi]
- Chip Package Co-Design of a Heterogeneously Integrated 2.45GHz CMOS VCO using Embedded Passives in a Silicon PackageGhanshyam Nayak, P. R. Mukund. 627-630 [doi]
- A Tuned Wideband LNA in 0.25?I m IBM Process For RF Communication ApplicationsM. Benmansour, P. R. Mukund. 631-634 [doi]
- A Low Noise Current-mode Readout circuit for CMOS Image Sensing ApplicationsTejasvi Das, P. R. Mukund. 635-638 [doi]
- Sizing Consideration for Leakage Control TransistorF. Farbiz, M. Farazian, M. Emadi, K. Sadeghi. 639-641 [doi]
- A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation FrameworkSukumar Jairam, C. Venkatesh, Navakanta Bhat, Shyam Singh, Rudra Pratap. 642-645 [doi]
- Analytical Expressions For Static Characteristics of Submicron CMOS InvertersShrutin Ulman. 646-649 [doi]
- Real Time Dynamic Voltage Scaling For Embedded SystemsVenkat Rao, Gaurav Singhal, Anshul Kumar. 650-653 [doi]
- Designing Leakage Aware MultipliersM. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishnan. 654-657 [doi]
- On Maximum Current Estimation in CMOS Digital CircuitsDainius Ciuplys, Per Larsson-Edefors. 658-661 [doi]
- Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation StudiesAnurag Chaudhry, M. Jagadesh Kumar. 662-665 [doi]
- Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched CapacitorsAshis Kumar Mal, Anindya Sundar Dhar. 666-669 [doi]
- Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral SynthesisAshok K. Murugavel, N. Ranganathan. 670 [doi]
- An ASIC Implementation of Kohonen s Map Based Color Image CompressionN. Sudha. 677-680 [doi]
- A Compact Low-Power Buffer Amplifier with Dynamic Bias Control TechniqueChih-Jen Yen, Wen-Yaw Chung, Mely Chen Chi. 681-684 [doi]
- Preventing Crosstalk Delay using Fibonacci RepresentationMadhu Mutyam. 685-688 [doi]
- An Area-Efficient Pipelined Array Architecture for Euclidean Distance Transformation and Its FPGA ImplementationN. Sudha. 689-692 [doi]
- The Nostrum Backbone - a Communication Protocol Stack for Networks on ChipMikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar, Axel Jantsch. 693-696 [doi]
- VLSI Architecture of Centroid Tracking Algorithms for Video TrackerManvendra Singh, B. S. Chauhan, N. K. Sharma. 697-700 [doi]
- A Narrow Pulse- Suppressing Filter For Input BufferPradip Mandal. 701-704 [doi]
- Improved Approach for Noise Propagation to Identify Functional Noise ViolationsSachin Shrivastava, Dhanoop Varghese, Vikas Narang, N. V. Arvind. 705-708 [doi]
- An Efficient Approach to Crosstalk Noise Analysis at Multiple Operating ModesSreeram Chandrasekar, Sachin Shrivastava, Ajoy Mandal, Sornavalli Ramanathan. 709-712 [doi]
- Energy Model Based Macrocell Placement for Wirelength MinimizationStelian Alupoaei, Srinivas Katkoori. 713-716 [doi]
- NoCGEN: A Template Based Reuse Methodology for Networks on Chip ArchitectureJeremy Chan, Sri Parameswaran. 717-720 [doi]
- Net Buffering in the Presence of Multiple Timing ViewsRajeev Murgai. 721-726 [doi]
- Path Based Approach for Crosstalk Delay AnalysisN. V. Arvind, K. A. Rajagopal, H. S. Ajith, Das Suparna. 727-730 [doi]
- Carry Circuitry for LUT-Based FPGAVarun Jindal, Alpana Agarwal. 731-734 [doi]
- An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimationMinoru Watanabe, Fuminori Kobayashi. 735 [doi]
- On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data CompressionIrith Pomeranz, Sudhakar M. Reddy. 741-744 [doi]
- ILP Models for Energy and Transient Power Minimization During Behavioral SynthesisSaraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi. 745-748 [doi]
- Cycle-Accurate Energy Model and Source-Independent Characterization Methodology for Embedded ProcessorsSyed Saif Abrar. 749-752 [doi]
- Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in MemoriesRajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar. 753-756 [doi]
- Synthesis of Full-Adder Circuit Using Reversible LogicHafiz Md. Hasan Babu, Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury. 757-760 [doi]
- Performance Analysis of Inter Cluster Communication Methods in VLIW ArchitectureSourabh Saluja, Anshul Kumar. 761-764 [doi]
- Boolean Decomposition Using Two-literal DivisorsNilesh Modi, Jordi Cortadella. 765-768 [doi]
- An Efficient Method to Generate Test Vectors for Combinational Cell VerificationNirav Patel, M. Srihari, Pooja Maheswari, G. N. Nandakumar. 769-772 [doi]
- Design of an Application Specific Instruction Set Processor for Parametric Speech SynthesisRavi Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Raj Singh, Chandra Shekhar. 773-775 [doi]
- OaSis: An Application Specific Operating System for an Embedded EnvironmentGurashish Singh Brar, Susmit Biswas, Sudipta Kundu, Arijit Mukhopadhyay, Pratik Worah, Anupam Basu. 776-779 [doi]
- Synthesis of Application Specific Multiprocessor Architectures for Process NetworksBasant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan. 780-783 [doi]
- Enhancing SAT-based Bounded Model Checking using Sequential Logic ImplicationsRajat Arora, Michael S. Hsiao. 784-787 [doi]
- Reset Careabouts in a SoC DesignSubrangshu Das, Subash G. Chandar, Ashutosh Tiwari. 788 [doi]
- Building Giga-Transistor [Enterprise] MicroprocessorsRaman Srinivas. 801 [doi]
- Device Reliability and Failure Mechanisms Related to Gate Dielectrics and InterconnectsM. K. Radhakrishnan. 805-808 [doi]
- ESD protection for the deep sub micron regime - a challenge for design methodologyHarald Gossner. 809 [doi]
- Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral ModelingTushar S. Shelar, G. S. Visweswaran. 821-826 [doi]
- A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar TransistorsM. Jagadesh Kumar, Vinod Parihar. 827-831 [doi]
- A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOIRajiv V. Joshi, K. Kroell, Ching-Te Chuang. 832 [doi]
- High-Performance Power Grids For Nanometer TechnologiesSachin S. Sapatnekar. 839-844 [doi]
- On-chip networks: A scalable, communication-centric embedded system design paradigmJörg Henkel, Wayne Wolf, Srimat T. Chakradhar. 845 [doi]
- Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner TreesGary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji. 855-862 [doi]
- An Area-Efficient Router for the Data-Intensive Architecture (DIVA) SystemSumit D. Mediratta, Jeff Sondeen, Jeffrey T. Draper. 863-868 [doi]
- Estimating Pre-Placement FPGA Interconnection RequirementsPariVallal Kannan, Dinesh Bhatia. 869 [doi]
- Digital Design: The components of a new paradigmRajat Gupta. 877 [doi]
- Random Access Scan: A solution to test power, test data volume and test timeDong Hyun Baik, Kewal K. Saluja, Seiji Kajihara. 883-888 [doi]
- Comparison of Effectiveness of Current Ratio and Delta-IDDQ TestsSagar S. Sabade, D. M. H. Walker. 889-894 [doi]
- At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented MemoriesXiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee. 895-900 [doi]
- Integrating Self Testability with Design Space Exploration by a Controller based Estimation TechniqueM. S. Gaur, Mark Zwolinski. 901-906 [doi]
- Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model CheckingGethin J. Norman, David Parker, Marta Z. Kwiatkowska, Sandeep K. Shukla. 907 [doi]
- Application Specific Instruction Set Processors: Redefining Hardware-Software BoundaryChandra Shekhar, Raj Singh, A. S. Mandal, S. C. Bose, Ravi Saini, Pramod Tanwar. 915 [doi]
- Synthesis-driven Exploration of Pipelined Embedded ProcessorsPrabhat Mishra, Arun Kejariwal, Nikil Dutt. 921-926 [doi]
- Cosynthesis of multiprocessor architectures with high availabilityS. Chakraverty. 927-932 [doi]
- Instruction-Based Delay Fault Self-Testing of Processor CoresVirendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara. 933 [doi]
- Analog/RF Physical Layer Issues For UWB SystemsRamesh Harjani, Jackson Harvey, Robert Sainati. 941 [doi]
- Katha-Mala: A Voice Output Communication Aid for the Children with Severe Speech and Multiple Disorders (SSMI)Arijit Mukhopadhyay, Saptarshi Biswas, Pratik Worah, Ramasish Das, Susmit Biswas, Anupam Basu. 951 [doi]
- High-Speed Optoelectronics Receivers in SiGeAmit Gupta, Steven P. Levitan, Leo Selavo, Donald M. Chiarulli. 957 [doi]
- Ant Colony Optimization Technique for Macrocell Overlap RemovalStelian Alupoaei, Srinivas Katkoori. 963-968 [doi]
- Constrained Floorplanning with WhitespaceYan Feng, Dinesh P. Mehta. 969-974 [doi]
- Floorplan Classification AlgorithmsKun Gao, Dinesh P. Mehta. 975-980 [doi]
- Maximum Multiplicity Distributions for Length Prediction Driven PlacementPranav Anbalagan, Jeffrey A. Davis. 981 [doi]
- Computing Silent Gate Models for Noise Analysis from Slew and Delay TablesShabbir H. Batterywala, Narendra V. Shenoy. 989-994 [doi]
- Application of Wavelets and Generalized Pencil-Of-Function Method for the Extraction of Noise Current Spectrum and Simulation of Simultaneous Switching NoiseRohan Mandrekar, Madhavan Swaminathan, Sungjun Chun. 995-1000 [doi]
- Dynamic Noise Margin: Definitions and ModelLi Ding 0002, Pinaki Mazumder. 1001 [doi]
- Advanced LCD Timing Controller IC with Memory-Assisted Response Time CompensationRichard McCartney, Nikhil Balram. 1009 [doi]
- Concurrent RF Test Using Optimized Modulated RF StimuliSasikumar Cherubal, Ramakrishna Voorakaranam, Abhijit Chatterjee, John Mclaughlin, Jason L. Smith, David M. Majernik. 1017-1022 [doi]
- A Current Sensor for On-Chip, Non-Intrusive Testing of RF SystemsAntonija Soldo, Anand Gopalan, P. R. Mukund, Martin Margala. 1023-1026 [doi]
- A Built-in-Self-Test Scheme for Digital to Analog ConvertersSunil Rafeeque, Vinita Vasudevan. 1027 [doi]
- CMOS Circuit Design for Minimum Dynamic Power and Highest SpeedTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell. 1035-1040 [doi]
- Dynamic Power Optimization of Interactive SystemsLin Zhong, Niraj K. Jha. 1041-1047 [doi]
- A Framework for Low Power Audio DesignNikolaus Voß, Bärbel Mertsching. 1048 [doi]
- An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA ImplementationT. K. Priya, K. Sridharan. 1057-1062 [doi]
- VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera DesignSaraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa. 1063 [doi]
- A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion EstimationKavish Seth, P. Rangarajan, S. Srinivasan, V. Kamakoti, V. Bala Kuteshwar. 1071-1076 [doi]
- An Architecture for Motion Estimation in the Transform DomainJ. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf. 1077-1082 [doi]
- A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converterAleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto. 1083 [doi]