Alpana Agarwal - researchr alias

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Viewing Publication 1 - 20 from 20

2022

A Scalable Fully-Digital Differential Analog Voltage ComparatorAshima Gupta, Anil Singh, Alpana Agarwal. jcsc, 31(4), 2022. [doi]

Functional validation of highly synthesizable voltage comparator on FPGAAshima Gupta, Anil Singh, Manu Bansal, Alpana Agarwal. integration, 84:151-158, 2022. [doi]

A Machine Learning Driven PVT-Robust VCO with Enhanced Linearity RangeNaveen Kandpal, Anil Singh, Alpana Agarwal. cssp, 41(8):4275-4292, 2022. [doi]

Intra and inter-patient arrhythmia classification using feature fusion with novel feature set based on fractional-order and fibonacci seriesAmandeep Kaur, Sanjay Kumar, Ravinder Agarwal, Alpana Agarwal. bspc, 72(Part):103365, 2022. [doi]

A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOSJagdeep Kaur Sahani, Anil Singh, Alpana Agarwal. cssp, 41(3):1299-1323, 2022. [doi]

A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillatorJagdeep Kaur Sahani, Anil Singh, Alpana Agarwal. ijcta, 50(8):2900-2912, 2022. [doi]

2021

Bidirectional transfer learning model for sentiment analysis of natural languageShivani Malhotra, Vinay Kumar, Alpana Agarwal. jaihc, 12(11):10267-10287, 2021. [doi]

2020

2019

Highly-digital voltage scalable 4-bit flash ADCAshima Gupta, Anil Singh, Alpana Agarwal. iet-cds, 13(1):91-97, 2019. [doi]

Fast digital foreground gain error calibration for pipelined ADCJupinder Kaur, Prince Prabhakar, Anil Singh, Alpana Agarwal. iet-cds, 13(2):219-225, 2019. [doi]

A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent SystemsJagdeep Kaur Sahani, Anil Singh, Alpana Agarwal. intellisys 2020: 266-275 [doi]

2017

A Digital-Based Low-Power Fully Differential ComparatorAnil Singh, Ayushi Goel, Alpana Agarwal. jcsc, 26(1):1-12, 2017. [doi]

Low-power 10-bit 100 MS/s pipelined ADC in digital CMOS technologyAnil Singh, Veena Rawat, Alpana Agarwal. iet-cds, 11(6):589-596, 2017. [doi]

2013

A Combined CMOS Reference Circuit with Supply and Temperature CompensationMadhusoodan Agrawal, Alpana Agarwal. vdat 2013: 177-184 [doi]

2011

Synthesis of Analog IC Building BlocksAlpana Agarwal, Chandra Shekhar. isvlsi 2011: 361-362 [doi]

2008

Figure-of-Merit-Based Area-Constrained Design of Differential AmplifiersAlpana Agarwal, Chandra Shekhar. vlsi, 2008, 2008. [doi]

2004

Carry Circuitry for LUT-Based FPGAVarun Jindal, Alpana Agarwal. vlsid 2004: 731-734 [doi]

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