Table of Contents

• Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks UsageAdel Dokhanchi, Ali Jahanian, Esfandiar Mehrshahi, M. Taghi Teimoori. 1-6 [doi]
• High Level Power Estimation Models for FPGAsAvinash Lakshminarayana, Sumit Ahuja, Sandeep K. Shukla. 7-12 [doi]
• The Study of a Dynamic Reconfiguration Manager for Systems-on-ChipMatthias Kühnle, Alisson Vasconcelos De Brito, Christoph Roth, Konstantinos Dagas, Jürgen Becker. 13-18 [doi]
• A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-ChipChaochao Feng, Minxuan Zhang, Jinwen Li, Jiang Jiang, Zhonghai Lu, Axel Jantsch. 19-24 [doi]
• Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical LinksFlorian Darve, Abbas Sheibanyrad, Pascal Vivet, Frédéric Pétrot. 25-30 [doi]
• Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCsSurajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman. 31-36 [doi]
• Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFETRamesh Vaddi, Sudeb Dasgupta, R. P. Agarwal. 37-42 [doi]
• Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS CircuitsGanesh C. Patil, S. Qureshi. 43-48 [doi]
• An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise ToleranceShashank Parashar, Chaudhry Indra Kumar, Manisha Pattanaik. 49-53 [doi]
• A DRAM Centric NoC Architecture and Topology Design ApproachCiprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli. 54-59 [doi]
• A Method for Integrating Network-on-Chip Topologies with 3D ICsM. Pawan Kumar, Anish S. Kumar, Srinivasan Murali, Luca Benini, Kamakoti Veezhinathan. 60-65 [doi]
• A NoC Traffic Suite Based on Real ApplicationsWeichen Liu, Jiang Xu, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Wei Zhang, Mahdi Nikdast, Zhehui Wang. 66-71 [doi]
• 500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC Anusmriti Menka Sukhwani, Vinay Bhaskar Chandratre, Megha Thomas, C. K. Pithawa, Vangmayee Sharda. 72-77 [doi]
• A 16-Gbps 9mW Transmitter with FFE in 90nm CMOS Technology for Off-Chip CommunicationS. R. Sant, S. S. Waikar, M. Dave, Maryam Shojaei Baghini, D. K. Sharma. 78-83 [doi]
• A Response Surface Method for Design Space Exploration and Optimization of Analog CircuitsArnab Khawas, Amitava Banerjee, Siddhartha Mukhopadhyay. 84-89 [doi]
• A New Wirelength Model for Analytical PlacementB. N. B. Ray, Shankar Balachandran. 90-95 [doi]
• Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB PlacementYiqiang Sheng, Atsushi Takahashi, Shuichi Ueno. 96-101 [doi]
• Statistical Timing-Based Post-Placement Leakage RecoveryEvriklis Kounalakis, Christos P. Sotiriou, Vassilis Zebilis. 102-107 [doi]
• A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHzArnab K. Biswas, A. Bulusu, S. DasGupta. 108-113 [doi]
• Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADCManas Kumar Hati, Tarun Kanti Bhattacharyya. 114-119 [doi]
• ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean OptimizationRobert Wille, Hongyan Zhang, Rolf Drechsler. 120-125 [doi]
• Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate StructuresMatthew Morrison, Nagarajan Ranganathan. 126-131 [doi]
• A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS TechnologyNaveen Kumar Kancharapu, Marshnil Vipin Dave, Veerraju Masimukkula, Maryam Shojaei Baghini, Dinesh Kumar Sharma. 132-137 [doi]
• A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing CongestionZohre Mohammadi-Arfa, Ali Jahanian. 138-143 [doi]
• Layer-Aware Design Partitioning for Vertical Interconnect MinimizationYa-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang. 144-149 [doi]
• Requirement Evolution Management: A Systematic ApproachAnsuman Banerjee. 150-155 [doi]
• Equivalence Checking of Array-Intensive ProgramsChandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal. 156-161 [doi]
• Application of Formal Methods for System-Level Verification of Network on ChipVinitha Arakkonam Palaniveloo, Arcot Sowmya. 162-169 [doi]
• A Markov Performance Model for Buffered Protocol DesignJing Cao, Albert Nymeyer. 170-175 [doi]
• Low Power Motion Estimation with Probabilistic ComputingCharvi Dhoot, Vincent J. Mooney, Lap-Pui Chau, Shubhajit Roy Chowdhury. 176-181 [doi]
• Low Power Probabilistic Floating Point Multiplier DesignAman Gupta, Satyam Mandavalli, Vincent J. Mooney, Keck Voon Ling, Arindam Basu, Henry Johan, Budianto Tandianus. 182-187 [doi]
• TSV-aware Scan Chain Reordering for 3D ICAyan Datta, Charudhattan Nagarajan, Susmita Sur-Kolay. 188-193 [doi]
• Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVsMichael Buttrick, Sandip Kundu. 194-199 [doi]
• Lithography Constrained Placement and Post-Placement Layout Optimization for ManufacturabilityNishant Dhumane, Sudheendra K. Srivathsa, Sandip Kundu. 200-205 [doi]
• A Simulation Based Buffer Sizing Algorithm for Network on ChipsAnish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli. 206-211 [doi]
• Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage AssignmentShuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai. 212-217 [doi]
• Enhanced Redundant via Insertion with Multi-via MechanismsTing-Feng Chang, Tsang-Chi Kan, Shih Hsien Yang, Shanq-Jang Ruan. 218-223 [doi]
• Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter ChainRaghavan Kumar, Vinay C. Patil, Sandip Kundu. 224-229 [doi]
• Impact of Circuit Degradation on FPGA Design SecurityHan-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan. 230-235 [doi]
• Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAMKarthik Swaminathan, Ravindhiran Mukundrajan, Niranjan Soundararajan, Vijaykrishnan Narayanan. 236-241 [doi]
• Metallic-CNT and Non-uniform CNTs Tolerant Design of CNFET-based Circuits Using Independent N2-Transistor StructuresBehnam Ghavami, Mohsen Raji, Hossein Pedram. 242-247 [doi]
• On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester MeasurementsVikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu. 248-253 [doi]
• Modeling and Analysis of Thermal Effects in Optical Networks-on-ChipYaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu. 254-259 [doi]
• A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoCWeichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang. 260-265 [doi]
• Characterizing the L1 Data Cache s Vulnerability to Transient Errors in Chip-MultiprocessorsLi Tang, Shuai Wang, Jie Hu, Xiaobo Sharon Hu. 266-271 [doi]
• AIFSP: An Adaptive Instruction Flow Stream ProcessorYaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang, Shenggang Chen. 272-277 [doi]
• A Novel Binding Algorithm to Reduce Critical Path Delay During High Level SynthesisSharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan. 278-283 [doi]
• Power Efficient Multiplexer Using DLDFF Synchronous CounterP. Rajshekar, M. Malathi. 284-289 [doi]
• A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of DatapathsD. S. Harish Ram, M. C. Bhuvaneswari, S. M. Logesh. 290-295 [doi]
• Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative DecoderDeepak Dasalukunte, Fredrik Rusek, Viktor Öwall. 296-300 [doi]
• Application-Specific Energy Optimization of General-Purpose Datapath InterconnectBabak Hidaji, Salar Alipour, Kasyab P. Subramaniyan, Per Larsson-Edefors. 301-306 [doi]
• Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary DomainVarun Vasudevan, Vinay Sheshadri, Sivarama Krishnan R., K. S. Vasundara Patel. 307-312 [doi]
• Verification of Register Transfer Level Low Power TransformationsChandan Karfa, Chitta Mandal, Dipankar Sarkar. 313-314 [doi]
• Gate Sizing Minimizing Delay and AreaGracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis. 315-316 [doi]
• A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic BiochipsPranab Roy, Rajesh Mandal, Hafizur Rahaman, Parthasarathi Dasgupta. 317-318 [doi]
• Post-Synthesis Circuit Techniques for Runtime Leakage ReductionSeetal Potluri, Nitin Chandrachoodan, V. Kamakoti. 319-320 [doi]
• A Global Optimization for Scan Chain Insertion at the RT-levelLilia Zaourar, Yann Kieffer, Chouki Aktouf. 321-322 [doi]
• A Design of Experiment Based Approach to Variance Optimal Design of CMOS OpAmpArnab Khawas, Siddhartha Mukhopadhyay. 325-326 [doi]
• An Analytical Drain Current Model for Short-Channel Triple-Material Double-Gate MOSFETsHarshit Agnihotri, Abhishek Ranjan, Pramod Kumar Tiwari, S. Jit. 327-328 [doi]
• Design to Introduce On-chip Fine Tunability in Analog Active InductorGarima Kapur, Kapil Bhola, C. M. Markan. 329-330 [doi]
• On the Potentials of FinFETs for Asynchronous Circuit DesignFataneh Jafari, Mahdi Mosaffa, Siamak Mohammadi. 331-332 [doi]
• Modeling Study of Impact of Surface Roughness on Flicker Noise in MOSFETPrafulla Galphade, Rasika Dhavse. 333-334 [doi]
• Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm OptimizationPradip Kumar Sahu, Putta Venkatesh, Sunilraju Gollapalli, Santanu Chattopadhyay. 335-336 [doi]
• Preprocessing-Based Run-Time Mapping of Applications on NoC-based MPSoCsSamarth Kaushik, Amit Kumar Singh, Thambipillai Srikanthan. 337-338 [doi]
• A Design Space Exploration Methodology for Application Specific MPSoC DesignAmit Kumar Singh, Akash Kumar, Thambipillai Srikanthan. 339-340 [doi]
• Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip SynthesisSoumya J., Putta Venkatesh, Santanu Chattopadhyay. 341-342 [doi]
• Intelligent On/Off Link Management for On-chip NetworksAndreas G. Savva, Theocharis Theocharides, Vassos Soteriou. 343-344 [doi]
• Low-Power, Energy-Efficient Full Adder for Deep-Submicron DesignMallikarjuna Rao Nimmagadda, Ajit Pal. 345-346 [doi]
• Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM DecompositionB. Sandeep Kumar, Vikram Pudi, K. Sridharan. 347-348 [doi]
• A Prefix Based Reconfigurable AdderChetan Kumar V., Sai Phaneendra P., S. Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas. 349-350 [doi]
• Architectures for Simultaneous Coding and Encryption Using Chaotic MapsAmit Pande, Joseph Zambreno, Prasant Mohapatra. 351-352 [doi]
• Low Power Asynchronous Sigma-Delta Modulator Using Hysteresis Level ControlAnita Arvind Deshmukh, Raghevendra Deshmukh, Rajendra Patrikar. 353-354 [doi]
• Power-Efficient Inter-Layer Communication Architectures for 3D NoCAmir-Mohammad Rahmani, Khalid Latif 0002, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 355-356 [doi]
• Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated CircuitsSantanu Kundu, Santanu Chattopadhyay. 357-358 [doi]
• Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier SystemsDeepak Dasalukunte, Fredrik Rusek, John B. Anderson, Viktor Öwall. 359-360 [doi]
• Synthesis of Analog IC Building BlocksAlpana Agarwal, Chandra Shekhar. 361-362 [doi]
• Design and Analysis of Pairing Based Cryptographic Hardware for Prime FieldsSantosh Ghosh. 363-364 [doi]
• Study and Analysis of Power Optimization Techniques for Embedded SystemsG. Indumathi, K. V. Ramakrishnan. 365-366 [doi]
• Next Generation Smart Home Systems Using Hardware Acceleration TechniquesDavid Fuschelberger, Ioannis Pyrounakis, Tasos Dagiuklas, Nikolaos S. Voros, Carlos Ribeiro. 367-368 [doi]
• Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture FamilyChia-I Chen, Juinn-Dar Huang. 369-370 [doi]
• Thermal Analysis of Advanced 3D Stacked SystemsKameswar Rao Vaddina, Amir-Mohammad Rahmani, Khalid Latif 0002, Pasi Liljeberg, Juha Plosila. 371-372 [doi]