Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai. Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India. pages 212-217, IEEE Computer Society, 2011. [doi]
Abstract is missing.