Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment - researchr publication authors

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Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai. Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India. pages 212-217, IEEE Computer Society, 2011. [doi]

This author has not been identified. Look up 'Shuzhe Zhou' in GoogleThis author has not been identified. Look up 'Hailong Yao' in GoogleThis author has not been identified. Look up 'Qiang Zhou' in GoogleThis author has not been identified. Look up 'Yici Cai' in Google

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