Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal. A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems. In Yaxin Bi, Rahul Bhatia, Supriya Kapoor, editors, Intelligent Systems and Applications - Proceedings of the 2019 Intelligent Systems Conference, IntelliSys 2019, London, UK, September 5-6, 2019, Volume 1. Volume 1037 of Advances in Intelligent Systems and Computing, pages 266-275, Springer, 2019. [doi]
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