Narender Hanchate - researchr alias

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Viewing Publication 1 - 10 from 10

2022

Improving Chip Design Performance and Productivity Using Machine LearningNarender Hanchate. ispd 2022: 51 [doi]

2007

Integrated Gate and Wire Sizing at Post Layout LevelNarender Hanchate, Nagarajan Ranganathan. isvlsi 2007: 225-232 [doi]

Statistical Gate Sizing for Yield Enhancement at Post Layout LevelNarender Hanchate, Nagarajan Ranganathan. isvlsi 2007: 245-252 [doi]

2006

A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizingNarender Hanchate, Nagarajan Ranganathan. todaes, 11(3):711-739, 2006. [doi]

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise OptimizationNarender Hanchate, Nagarajan Ranganathan. isqed 2006: 92-97 [doi]

Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game TheoryNarender Hanchate, Nagarajan Ranganathan. TC, 55(8):1011-1023, 2006. [doi]

A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk NoiseNarender Hanchate, Nagarajan Ranganathan. vlsid 2006: 283-290 [doi]

CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDLNagarajan Ranganathan, Ravi Namballa, Narender Hanchate. isvlsi 2006: 329-334 [doi]

2004

LECTOR: a technique for leakage reduction in CMOS circuitsNarender Hanchate, Nagarajan Ranganathan. tvlsi, 12(2):196-205, 2004.

A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked TransistorsNarender Hanchate, Nagarajan Ranganathan. vlsid 2004: 228-233 [doi]

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