A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors - researchr publication

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Narender Hanchate, Nagarajan Ranganathan. A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. In 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India. pages 228-233, IEEE Computer Society, 2004. [doi]

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