Narender Hanchate, Nagarajan Ranganathan. A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. In 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India. pages 228-233, IEEE Computer Society, 2004. [doi]
@inproceedings{HanchateR04:0, title = {A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors}, author = {Narender Hanchate and Nagarajan Ranganathan}, year = {2004}, url = {http://csdl.computer.org/comp/proceedings/vlsid/2004/2072/00/20720228abs.htm}, researchr = {https://researchr.org/publication/HanchateR04%3A0}, cites = {0}, citedby = {0}, pages = {228-233}, booktitle = {17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India}, publisher = {IEEE Computer Society}, isbn = {0-7695-2072-3}, }