Table of Contents

• Advanced Channel Decoding Algorithms and Their Implementation for Future Communication SystemsNorbert Wehn. 3 [doi]
• Multiprocessor Systems-on-ChipsWayne Wolf. 4 [doi]
• Floorplanning Based on Particle Swarm OptimizationTsung-Ying Sun, Sheng-Ta Hsieh, Hsiang-Min Wang, Cheng-Wei Lin. 7-11 [doi]
• Enhanced Dual Strategy based VLSI Architecture for Computing Pseudo Inverse of Channel Matrix in a MIMO Wireless SystemZahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan. 12-17 [doi]
• Adaptive Porting of Analog IPs with Reusable Conservative PropertiesTakashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani. 18-23 [doi]
• VLSI Design Exchange with Intellectual Property Protection in FPGA Environment Using both Secret and Public-Key CryptographyWael Adi, Rolf Ernst, Bassel Soudan, Abdulrahman Hanoun. 24-32 [doi]
• Metal Fix and Power Network Repair for SOCQing K. Zhu, Paige Kolze. 33-37 [doi]
• Multi-SP: A Representation with United Rectangles for Analog Placement and RoutingNing Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake. 38-43 [doi]
• Formulating the Empirical Strategies in Module Generation of Analog MOS LayoutTan Yan, Shigetoshi Nakatake, Takashi Nojima. 44-49 [doi]
• An Integer Linear Programming Based Approach to Simultaneous Memory Space Partitioning and Data Allocation for Chip MultiprocessorsOzcan Ozturk, G. Chen, Mahmut T. Kandemir, Mustafa Karaköy. 50-58 [doi]
• High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold VoltagesZhiyu Liu, Volkan Kursun. 59-64 [doi]
• High performance service-time-stamp computation for WFQ IP packet schedulingColm McKillen, Sakir Sezer, Xin Yang. 65-70 [doi]
• Synthesis of Pipelined SRSL CircuitsRashad Oreifej, Abdelhalim Alsharqawi, Abdel Ejnioui. 71-76 [doi]
• An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS StandardRomualdo Begale Prudencio, Leandro Soares Indrusiak, Manfred Glesner. 77-84 [doi]
• Autonomous Realization of Boeing/JPL Sensor Electronics based on Reconfigurable System-on-Chip TechnologyEvangelos F. Stefatos, Tughrul Arslan, Didier Keymeulen, Ian Ferguson. 85-90 [doi]
• Defect-Aware Design Paradigm for Reconfigurable ArchitecturesRahul Jain, Anindita Mukherjee, Kolin Paul. 91-96 [doi]
• New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic CircuitsMichael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker. 97-102 [doi]
• A Soft++ eFPGA Physical Design Approach with Case Studies in 180nm and 90nmVictor Aken Ova, Resve Saleh. 103-108 [doi]
• QUKU: A Two-Level Reconfigurable ArchitectureSunil Shukla, Neil W. Bergmann, Jürgen Becker. 109-116 [doi]
• Space-Saving Layout for Passive ComponentsPäivi H. Karjalainen, Pekka Heino. 117-121 [doi]
• A Novel Low Power Multilevel Current Mode Interconnect SystemSupreet Joshi, Dinesh Sharma. 122-127 [doi]
• The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read ChannelSheng-Jang Lin, I-Shun Chen, Bo-Wei Chen, Feng-Hsiang Lo. 128-132 [doi]
• Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian LearningMiguel Figueroa, Esteban Matamala, Gonzalo Carvajal, Seth Bridges. 133-140 [doi]
• Verification of Scheduling in High-level SynthesisChandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade. 141-146 [doi]
• An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip TestingMing Li, Wen-Ben Jone, Qing-An Zeng. 147-152 [doi]
• An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-ChipXiaoyu Ruan, Rajendra S. Katti. 153-158 [doi]
• Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAsKatarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker. 159-166 [doi]
• Design and Analysis of a Low Power VLIW DSP CoreChan-Hao Chang, Diana Marculescu. 167-172 [doi]
• High-Performance Noise-Robust Asynchronous CircuitsPankaj Golani, Peter A. Beerel. 173-178 [doi]
• A Low Power Lookup Technique for Multi-Hashing Network ApplicationsIlhan Kaya, Taskin Koçak. 179-184 [doi]
• A Low Power Pipelined Maximum Likelihood Detector for 4x4 QPSK MIMO Wireless Communication SystemsJ. H. Han, Ahmet T. Erdogan, Tughrul Arslan. 185-192 [doi]
• Optimal Periodical Memory Allocation for Logic-in-Memory Image ProcessorsMasanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi. 193-198 [doi]
• Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock GatingEsmail Amini, Mehrdad Najibi, Hossein Pedram. 193-199 [doi]
• Connection-oriented Multicasting in Wormhole-switched Networks on ChipZhonghai Lu, Bei Yin, Axel Jantsch. 205-2110 [doi]
• A Virtual Channel Network-on-Chip for GT and BE trafficNikolay Kavaldjiev, Gerard J. M. Smit, Pierre G. Jansen, Pascal T. Wolkotte. 211-216 [doi]
• Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional SignalingEthiopia Nigussie, Juha Plosila, Jouni Isoaho. 217-224 [doi]
• Nanowire Addressing in the Face of UncertaintyEric Rachlin, John E. Savage. 225-230 [doi]
• Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number GenerationRyuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita. 231-236 [doi]
• Finite State Machine Implementation with Single-Electron Tunneling TechnologyJialin Mi, Chunhong Chen. 237-241 [doi]
• PLAs in Quantum-dot Cellular AutomataXiaobo Sharon Hu, Michael Crocker, Michael T. Niemier, Minjun Yan, Gary H. Bernstein. 242-250 [doi]
• Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration ManagerPascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker. 251-256 [doi]
• Regular Routing Architecture for a LUT-based MPGAFrancisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer. 257-262 [doi]
• A new Multilevel Hierarchical MFPGA and its suitable configuration toolsZied Marrakchi, Hayder Mrabet, Habib Mehrez. 263-268 [doi]
• New non-volatile FPGA concept using Magnetic Tunneling JunctionNicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon. 269-276 [doi]
• Profile Directed Instruction Cache Tuning for Embedded SystemsKugan Vivekanandarajah, Thambipillai Srikanthan, Christopher T. Clarke. 277-282 [doi]
• Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level DesignYuriy Sheynin, Elena Suvorova, Felix Shutenko. 283-288 [doi]
• Fast Configuration of an Energy-Efficient Branch PredictorPeter Hallschmid, Resve Saleh. 289-294 [doi]
• Exploiting Software Pipelining for Network-on-Chip architecturesFeihui Li, Mahmut T. Kandemir, Ibrahim Kolcu. 295-302 [doi]
• An Efficient Algorithm for the Analysis of Cyclic CircuitsOsama Neiroukh, Stephen A. Edwards, Xiaoyu Song. 303-308 [doi]
• Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary AlgorithmsThomas Schlichter, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich. 309-316 [doi]
• Optimisation of the SHA-2 Family of Hash Functions on FPGAsRobert P. McEvoy, Francis M. Crowe, Colin C. Murphy, William P. Marnane. 317-322 [doi]
• A Novel Approach to Performance-Oriented Datapath Allocation and FloorplanningVijay Sundaresan, Ranga Vemuri. 323-328 [doi]
• CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDLNagarajan Ranganathan, Ravi Namballa, Narender Hanchate. 329-334 [doi]
• System Exploration of SystemC DesignsChristian Genz, Rolf Drechsler. 335-342 [doi]
• Reliability-Aware SOC Voltage Islands Partition and FloorplanShengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie. 343-348 [doi]
• Ultra-Low Energy Computing with Noise: Energy-Performance-Probability Trade-offsPinar Korkmaz, Bilge E. S. Akgul, Krishna V. Palem. 349-354 [doi]
• Delay and Energy Efficient Data Transmission for On-Chip BusesMadhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie. 355-360 [doi]
• Power-Oriented Delay Budgeting for Combinational CircuitsJialin Mi, Chunhong Chen. 361-366 [doi]
• Routing-Tree Construction with Concurrent Performance, Power and Congestion OptimizationAlkan Cengiz, Tom Chen. 367-372 [doi]
• Clock Gated Static Pulsed Flip-Flop (CGSPFF) in Sub 100 nm TechnologyA. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha. 373-377 [doi]
• Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor SystemsZhiyi Yu, Bevan M. Baas. 378-383 [doi]
• Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) TechnologyKiran Puttaswamy, Gabriel H. Loh. 384-392 [doi]
• Leakage-Aware SPM ManagementFeihui Li, Ozcan Ozturk, Guangyu Chen, Mahmut T. Kandemir, Ibrahim Kolcu. 393-398 [doi]
• Dependability Analysis of Nano-scale FinFET circuitsFeng Wang 0004, Yuan Xie, Kerry Bernstein, Yan Luo. 399-404 [doi]
• A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS TechnologyChua-Chin Wang, Gang-Neng Sung. 405-410 [doi]
• Multi-Level Buffer Block Planning and Buffer Insertion for Large Design CircuitsAli Jahanian, Morteza Saheb Zamani. 411-415 [doi]
• Effect of Glitches on the Efficiency of Components Region-Constrained Placement as a Fast Approach to Reduce FPGA s Dynamic Power ConsumptionSeyed E. Esmaeili, Nabil I. Khachab, Moustafa Y. Ghannam. 416-417 [doi]
• Towards a Faster Simulation of SystemC DesignsAli Habibi, Haja Moinudeen, Amer Samarah, Sofiène Tahar. 418-419 [doi]
• An Optimized BIST Architecture for FPGA Look-Up Table TestingMahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi. 420-421 [doi]
• Variation Aware Placement for FPGAsSuresh Srinivasan, Narayanan Vijaykrishnan. 422-423 [doi]
• A Regular Layout Approach for ASICsClaudio Menezes, Cristina Meinhardt, Ricardo Reis, Reginaldo Tavares. 424-425 [doi]
• Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-ChipJosé Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes. 426-427 [doi]
• Dual-Mode High-Speed Low-Energy Binary AdditionJohannes Grad, James E. Stine. 428-429 [doi]
• A Flexible Architecture For Block Turbo Decoders Using BCH Or Reed-Solomon Components CodesErwan Piriou, Christophe Jégo, Patrick Adde, Michel Jézéquel. 430-431 [doi]
• Transparent Management of Reconfigurable Hardware in Embedded Operating SystemsKrzysztof Kosciuszkiewicz, Krzysztof Kepa, Fearghal Morgan. 432-433 [doi]
• An open-source tool for simulation of partially reconfigurable systems using SystemCAlisson V. De Brito, Elmar U. K. Melcher, Wilson Rosas. 434-435 [doi]
• Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementationFlorent Berthelot, Fabienne Nouvel. 436-437 [doi]
• Self-Timed Thermally-Aware CircuitsDavid Fang, Filipp Akopyan, Rajit Manohar. 438-439 [doi]
• A New Protocol Stack Model for Network on ChipMasood Dehyadgari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi. 440-441 [doi]
• A Robust SynchronizerJun Zhou, David Kinniment, Gordon Russell, Alexandre Yakovlev. 442-443 [doi]
• Low Power Layered Space-Time Channel Detector Architecture for MIMO SystemsT. Takahashi, Ahmet T. Erdogan, Tughrul Arslan, J. H. Han. 444-445 [doi]
• Sensor-Driven Power Management: Enhancing Performance and Reliability of Autonomously Powered SystemsJosef Haid, Dietmar Scheiblhofer. 446-447 [doi]
• Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU SystemsHakduran Koc, Suleyman Tosun, Ozcan Ozturk, Mahmut T. Kandemir. 448-449 [doi]
• Compiler-Directed Management of Leakage Power in Software-Managed MemoriesGuangyu Chen, Feihui Li, Mahmut T. Kandemir, Ozcan Ozturk, I. Demirkiran. 450-451 [doi]
• A Parallel Architecture for Hardware Face DetectionTheo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin. 452-453 [doi]
• A VLSI GFP Frame Delineation CircuitCiaran Toal, Sakir Sezer, Xin Yang. 454-455 [doi]
• Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution NetworksItisha Chanodia, Dimitrios Velenis. 456-457 [doi]