CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL - researchr publication

researchr

You are not signed in
Sign in
Sign up

Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate. CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. In 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany. pages 329-334, IEEE Computer Society, 2006. [doi]

Abstract is missing.

runs on WebDSL