An Optimized BIST Architecture for FPGA Look-Up Table Testing - researchr publication

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Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi. An Optimized BIST Architecture for FPGA Look-Up Table Testing. In 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany. pages 420-421, IEEE Computer Society, 2006. [doi]

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