Chua-Chin Wang, Gang-Neng Sung. A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology. In 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany. pages 405-410, IEEE Computer Society, 2006. [doi]
Abstract is missing.