Narender Hanchate, Nagarajan Ranganathan. Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. In 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA. pages 92-97, IEEE Computer Society, 2006. [doi]
Abstract is missing.