CMOS Scaling for sub-90 nm to sub-10 nm - researchr publication

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Hiroshi Iwai. CMOS Scaling for sub-90 nm to sub-10 nm. In 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India. pages 30, IEEE Computer Society, 2004. [doi]

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