Joonhwan Yi - researchr alias

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Viewing Publication 1 - 13 from 13

2018

An interpolation method for strong barrel lens distortionChangwon Choi, Hyungkeun Lee, Joonhwan Yi. vc, 34(11):1479-1491, 2018. [doi]

2016

Register grouping for synthesis of clock gating logicInhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin. icicdt 2016: 1-4 [doi]

Modeling and performance analysis for a receiver-initiated MAC protocol in wireless sensor networksJoonhwan Yi, Hyungkeun Lee. ijdsn, 12(11), 2016. [doi]

2015

A Receiver-Initiated MAC Protocol for Wireless Sensor Networks Based on Tree TopologyInhye Park, Joonhwan Yi, Hyungkeun Lee. ijdsn, 2015, 2015. [doi]

Power modeling for digital circuits with clock gatingJoonhwan Yi, Jong-Gyu Kim. ieiceee, 12(24):20150817, 2015. [doi]

2012

Robust Coupling Delay Test SetsJoonhwan Yi, John P. Hayes. et, 28(3):375-388, 2012. [doi]

2011

A data flow optimization method for high speed MAC processing in an IEEE 802.16m modemKyung Won Kim, Joonhwan Yi, Seong-Jun Oh. ieiceee, 8(8):530-535, 2011. [doi]

2007

Industrial experience with cycle error computation of cycle-accurate transaction level modelsJungHee Lee, Joonhwan Yi. socc 2007: 155-158 [doi]

2006

Cycle error correction in asynchronous clock modeling for cycle-based simulationJungHee Lee, Joonhwan Yi. aspdac 2006: 460-465 [doi]

High-level delay test generation for modular circuitsJoonhwan Yi, John P. Hayes. tcad, 25(3):576-590, 2006. [doi]

2005

The Coupling Model for Function and Delay FaultsJoonhwan Yi, John P. Hayes. et, 21(6):631-649, 2005. [doi]

2002

High -level function and delay testing for digital circuitsJoonhwan Yi. PhD thesis, University of Michigan, USA, 2002. [doi]

2001

A fault model for function and delay testingJoonhwan Yi, John P. Hayes. ets 2001: 27-34 [doi]

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