Table of Contents

• A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technologyHwei-Yu Lee, Shen-Iuan Liu. 3-6 [doi]
• A 1.5V mixed signal biomedical SOC for implantable cardioverter defibrillatorsKilhwan Kim, Unsun Cho, Seunghyun Lim, Youngcheol Chae, Yunho Jung, Gunhee Han, Jaeseok Kim. 7-10 [doi]
• A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOSHwei-Yu Lee, I.-Hsin Wang, Shen-Iuan Liu. 11-14 [doi]
• A 1V CMOS low-noise amplifier with inductive resonated for 3.1-10.6GHz UWB wireless receiverZhe-Yang Huang, Che-Cheng Huang, Chun-Chieh Chen, Chung-Chih Hung. 15-18 [doi]
• Reconfigurable architecture for video applicationsChung-Jr Lian, Po-Chih Tseng, Tung-Chien Chen, Yu-wei Chang, Liang-Gee Chen. 21-24 [doi]
• A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOSSanu Mathew, David Harris, Mark Anders, Steven Hsu, Ram Krishnamurthy. 25-28 [doi]
• Design of cost-efficient memory-based FFT processors using single-port memoriesYao-Xian Yang, Jin-Fu Li, Hsiang-Ning Liu, Chin-Long Wey. 29-32 [doi]
• A compact pipelined architecture with high-throughput for context-based binary arithmetic codingChu Yu, Hwai-Tsu Hu. 33-36 [doi]
• A merged MuGFET and planar SOI processAndrew Marshall, C. Rinn Cleavelin, Weize Xiong, Christian Pacha, Gerhard Knoblinger, Klaus Von Armin, Thomas Schulz, Klaus Schruefer, Ken Matthews, Wolfgang Molzer, Paul Patruno, Christian Russ. 39-42 [doi]
• An efficient power reduction technique for flash ADCYuh-Shyan Hwang, Jeen-Fong Lin, Cheng-Chung Huang, Jiann-Jong Chen, Wen-Ta Lee. 43-46 [doi]
• A 250MHz 11BIT 20mW low-hold-pedestal CMOS fully differential track-and-hold circuitTsung-Sum Lee, Chi-Chang Lu, Jian-Ting Zhan. 47-50 [doi]
• Design of a SIMD multimedia SoC platformGuang-Huei Lin, Ya-Nan Wen, Xiao-Long Wu, Sao-Jie Chen, Yu Hen Hu. 51-54 [doi]
• Reconfigurable video motion estimation processorLiang Lu, John V. McCanny, Sakir Sezer. 55-58 [doi]
• Reduced computation and memory access for VBSME using pixel truncationAsral Bahari, Tughrul Arslan, Ahmet T. Erdogan. 59-62 [doi]
• An independent-gate FinFET SRAM cell for high data stability and enhanced integration densityZhiyu Liu, Sherif A. Tawfik, Volkan Kursun. 63-66 [doi]
• An incremental floorplanning algorithm for temperature reductionWon-Jin Kim, Ki-Seok Chung. 67-70 [doi]
• Surveillance camera SOC architecture using one-bit motion detection for portable applicationsJeong Hun Kim, Jeongwoo Park, Kwangjae Lee, Kyoungbum Kim, Kwang-Hyun Baek, Suki Kim. 71-74 [doi]
• An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSIMinoru Watanabe. 75-78 [doi]
• Intra-die process parameter variation and leakage analysis of cache at the microarchitectural levelManjari Agarwal, Praveen Elakkumanan, Ramalingam Sridhar. 79-82 [doi]
• Accelerating pattern matching for DPIJun Mu, Sakir Sezer, Gareth Douglas, Dwayne Burns, Emi Garcia, Mike Hutton, Kevin Cackovic. 83-86 [doi]
• A ZigBee compliant baseband and MAC processorSinae Ji, Woon Hong Kim, Chulho Chung, Jaeseok Kim. 87-90 [doi]
• Robust 3GHz CMOS low noise amplifier adapted for RFID receiversVarun V. Ramaswamy, Manjari Agarwal, Ramalingam Sridhar. 91-94 [doi]
• Improved decoding algorithm for high reliable reed muller codingCostas Argyrides, Dhiraj K. Pradhan. 95-98 [doi]
• A 1V-2.39mW capacitor-coupling resonated low noise amplifier for 3-5GHz ultra-wideband systemZhe-Yang Huang, Che-Cheng Huang, Chun-Chieh Chen, Chung-Chih Hung. 101-104 [doi]
• A fast pull-in scheme of plls using a triple path nonlinear phase frequency detectorMinglang Lin, Ahmet T. Erdogan, Tughrul Arslan, Adrian Stoica. 105-108 [doi]
• Low-power 1.25-GHZ signal bandwidth 4-bit CMOS analog-to-digital converter for high spurious-free dynamic range wideband communicationsMingzhen Wang, Chien-In Henry Chen. 109-112 [doi]
• A spur-reduction technique in a fully integrated CMOS frequency synthesizer for 5-GHz WLAN SOCYuan Sun, Liter Siek. 113-116 [doi]
• High defect tolerant low cost memory chipsCostas Argyrides, Ahmad A. Al-Yamani, Dhiraj K. Pradhan. 119-122 [doi]
• Programmable CRC circuit architectureCiaran Toal, Sakir Sezer, Xin Yang, Kieran McLaughlin, Dwayne Burns, Tiberiu Seceleanu. 123-126 [doi]
• Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architectureManhwee Jo, V. K. Prasad Arava, Hoonmo Yang, Kiyoung Choi. 127-130 [doi]
• Performance analysis of IEEE defined LDPC codes under various decoding algorithms and their implementation on a reconfigurable instruction cell architectureZahid Khan, Tughrul Arslan, Ahmet T. Erdogan, Sami Khawam, Ioannis Nousias, Mark Milward, Ying Yi. 131-134 [doi]
• Online thermal-aware scheduling for multiple clock domain CMPsAmirali Shayan Arani. 137-140 [doi]
• Design of ultra low power CML MUXs and latches with forward body biasHsiang-Ju Hsu, Ching-Te Chiu, Yarsun Hsu. 141-144 [doi]
• Low-power high-performance FinFET sequential circuitsSherif A. Tawfik, Volkan Kursun. 145-148 [doi]
• H.264/AVC decoder SoC towards the low cost mobile video playerSumek Wisayataksin, Dongju Li, Tsuyoshi Isshiki, Hiroaki Kunieda. 151-154 [doi]
• Industrial experience with cycle error computation of cycle-accurate transaction level modelsJungHee Lee, Joonhwan Yi. 155-158 [doi]
• Power evaluation of the arbitration policy for different on-chip bus based SoC platformPrakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan. 159-162 [doi]
• A wakeup rush current and charge-up time analysis method for programmable power-gating designsKaijian Shi, Jingsong Li. 163-165 [doi]
• Stochastic glitch elimination considering path correlationYouse Kim, Naeun Zang, Juho Kim. 169-172 [doi]
• Power estimation framework for single processor based SoC platformPrakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan. 173-176 [doi]
• Low-voltage zero quiescent current PFM boost converter for portable devicesHou-Ming Chen, Robert C. Chang, Chih-Liang Huang. 177-180 [doi]
• Mixed-VTH (MVT) CMOS circuit design for low power cell librariesJiun-Yi Lin, Li-Rong Wang, Chia-Lin Hu, Shyh-Jye Jou. 181-184 [doi]
• Early selection of system implementation choice among SoC, SoP and 3-D IntegrationRoshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen. 187-190 [doi]
• Device allocation on the SegBus platform based on communication scheduling cost minimizationTiberiu Seceleanu, Ville Leppänen, Olli Nevalainen. 191-196 [doi]
• Multilevel MPSOC simulation using an MDE approachRabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser. 197-200 [doi]
• Symbolic verification and error prediction methodologyChun-Jen Wei, Guang-Huei Lin, Ya-Nan Wen, Sao-Jie Chen, Yu Hen Hu. 201-204 [doi]
• A 65nm low power 2T1D embedded DRAM with leakage current reductionMu-Tien Chang, Po-Tsang Huang, Wei Hwang. 207-210 [doi]
• A 45nm dual-port SRAM with write and read capability enhancement at low voltageD. P. Wang, H. J. Liao, H. Yamauchi, Y. H. Chen, Y.-L. Lin, S.-H. Lin, D. C. Liu, H.-C. Chang, W. Hwang. 211-214 [doi]
• A versatile content addressable memory architectureXin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns. 215-218 [doi]
• A flexible two-layer external memory management for H.264/AVC decoderChang-Hsuan Chang, Ming-Hung Chang, Wei Hwang. 219-222 [doi]
• A prototype of a wireless-based test systemJing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Denq, Chien-Jung Chiu, Young-Wey Li, Chieh-Ming Chang. 225-228 [doi]
• X-Route: An X-architecture full-chip multilevel routerChenFeng Chang, YaoWen Chang. 229-232 [doi]
• Using power gating techniques in area-array SoC floorplan designChi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu. 233-236 [doi]
• QuteIP: An IP qualification framework for System on ChipHsing-Chih Hung, Ting-Hao Lin, Chung-Yang Huang. 237-240 [doi]
• A data-reuse scheme for avoiding unnecessary memory accesses in MPEG-4 ASP video decoderWei-Cheng Lin, Chung-Ho Chen. 243-246 [doi]
• Analysis and design of an efficient complementary energy path adiabatic logic for low-power system applicationsCihun-Siyong Alex Gong, Muh-Tian Shiue, Ci-Tong Hong, Chun-Hsien Su, Kai-Wen Yao. 247-250 [doi]
• Hardware architecture for lossless image compression based on context-based modeling and arithmetic codingXiaolin Chen, Nishan Canagarajah, Jose Luis Nunez-Yanez, Raffaele Vitulli. 251-254 [doi]
• A programmable FFT/IFFT/Windowing processor for multi standard DSL applicationsVijayavardhan Baireddy, Himamshu Khasnis, Rajesh Mundhada. 255-258 [doi]
• Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variabilityDarsun Tsiena, Chien Kuo Wang, William W. J. Wang, Yajun Ran, Philippe Hurat, Nishath Verghese. 261-268 [doi]
• Assertion based design error diagnosis for core-based SoCsMohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari. 269-272 [doi]
• Diagnosing scan chains using SAT-based diagnostic pattern generationJin-Fu Li, Feijun (Frank) Zheng, Kwang-Ting Cheng. 273-276 [doi]
• ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS processYuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng. 277-280 [doi]
• Hierarchical power delivery network analysis using Markov chainsPei-Yu Huang, Chih-Kang Lin, Yu-Min Lee. 283-286 [doi]
• Predictable system interconnects through accurate early wire characterizationI. Hatyrnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici. 287-290 [doi]
• Multiple clock domain synchronization for network on chip architecturesJabulani Nyathi, Souradip Sarkar, Partha Pratim Pande. 291-294 [doi]
• Area-driven decoupling capacitance allocation based on space sensitivity analysis for signal integrityJin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu. 295-298 [doi]
• Design of a downlink baseband receiver for IEEE 802.16E OFDMA mode in high mobilityKang-Chuan Chang, Jun-Wei Lin, Tzi-Dar Chiueh. 301-304 [doi]
• An all-digital phase-frequency tunable clock generator for wireless OFDM communications systemsJui-Yuan Yu, Juinn-Ting Chen, Mei-Hui Yang, Ching-Che Chung, Chen-Yi Lee. 305-308 [doi]
• A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applicationsBabita R. Jose, Jimson Mathew, P. Mythili, Dhiraj K. Pradhan. 309-312 [doi]
• Baseband design for passive semi-UWB wireless sensor and identification systemsZhuo Zou, Majid Baghaei Nejad, Hannu Tenhunen, Li-Rong Zheng. 313-316 [doi]