Multiple clock domain synchronization for network on chip architectures

Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande. Multiple clock domain synchronization for network on chip architectures. In 2007 IEEE International SOC Conference, Tampere, Finland, November 19-21, 2007. pages 291-294, IEEE, 2007. [doi]

Abstract

Abstract is missing.