Abstract is missing.
- Analyzing bridging faults impact on EEPROM cell arrayJ. M. Portal, A. Pérez. 3-8 [doi]
- Internal feedback bridging faults in combinational CMOS circuits: analysis and testingYukiya Miura, Shuichi Seno. 9-16 [doi]
- System-level DFT for consumer productsD. C. L. (Erik) van Geest, Frans G. M. de Jong. 19-24 [doi]
- A fault model for function and delay testingJoonhwan Yi, John P. Hayes. 27-34 [doi]
- Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variationsHerman J. Vermaak, Hans G. Kerkhoff. 35-41 [doi]
- Demodulation based testing of off-chip driver performanceWilfried Daehn. 42-47 [doi]
- Automated regression testing of CTI-systemsOliver Niese, Tiziana Margaria, Andreas Hagerer, Bernhard Steffen, Georg Brune, Werner Goerigk, Hans-Dieter Ide. 51-57 [doi]
- Reducing analogue fault-simulation time by using high-level modelling in dotss for an industrial designLiquan Fang, Guido Gronthoud, Hans G. Kerkhoff. 61-67 [doi]
- On-chip signal level evaluation for mixed-signal ICs using digital window comparatorsDaniela De Venuto, M. J. Ohletzo, Bruno Riccò. 68-72 [doi]
- The use of equivalent fault analysis to improve static D.C. fault diagnosis - a potentiometric DAC case studyMatthew Worsman, Mike W. T. Wong, Yim-Shu Lee. 73-78 [doi]
- A packet switching communication-based test access mechanism for system chipsMohsen Nahvi, André Ivanov. 81-86 [doi]
- System level diagnosis - a comparison of two alternative approachesMaisaa Khalil, Chantal Robach. 89-95 [doi]
- RTL design validation, DFT and test pattern generation for high defects coverageMarcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. 99-105 [doi]
- An implementation for test-time reduction in VLIW transport-triggered architecturesV. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff. 106-113 [doi]
- On hardware generation of random single input change test sequencesRené David, P. Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 117-123 [doi]
- Reusing scan chains for test pattern decompressionRainer Dorsch, Hans-Joachim Wunderlich. 124-132 [doi]
- A VHDL-based virtual test concept for pre-silicon test-program debugMarco Rona, Gunter Krampl. 135-139 [doi]
- Using at-speed BIST to test LVDS serializer/deserializer functionMagnus Eckersand, Fredrik Franzon, Ken Filliter. 140-145 [doi]