Table of Contents

• A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic CircuitsChing-Cheng Wang, Wai-Kei Mak. 1-9 [doi]
• IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCsNathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany. 1-9 [doi]
• Optimal Mapping for Near-Term Quantum Architectures based on Rydberg AtomsSebastian Brandhofer, Ilia Polian, Hans Peter Büchler. 1-7 [doi]
• Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session PaperHaoxing Ren, Saad Godil, Brucek Khailany, Robert Kirby, Haiguang Liao, Siddhartha Nath, Jonathan Raiman, Rajarshi Roy 0003. 1-6 [doi]
• pGRASS-Solver: A Parallel Iterative Solver for Scalable Power Grid Analysis Based on Graph Spectral SparsificationZhiqiang Liu, Wenjian Yu. 1-9 [doi]
• A Hybrid FPGA-ASIC Delayed Feedback Reservoir System to Enable Spectrum Sensing/Sharing for Low Power IoT Devices ICCAD Special Session PaperOsaze Shears, Kangjun Bai, Lingjia Liu 0001, Yang Yi 0002. 1-9 [doi]
• Automated Runtime-Aware Scheduling for Multi-Tenant DNN Inference on GPUFuxun Yu, Shawn Bray, Di Wang, Longfei Shangguan, Xulong Tang, Chenchen Liu, Xiang Chen. 1-9 [doi]
• FL-DISCO: Federated Generative Adversarial Network for Graph-based Molecule Drug Discovery: Special Session PaperDaniel Manu, Yi-sheng, Junhuan Yang, Jieren Deng, Tong Geng, Ang Li, Caiwen Ding, Weiwen Jiang, Lei Yang. 1-7 [doi]
• Heterogeneous Manycore Architectures Enabled by Processing-in-Memory for Deep Learning: From CNNs to GNNs: (ICCAD Special Session Paper)Biresh Kumar Joardar, Aqeeb Iqbal Arka, Janardhan Rao Doppa, Partha Pratim Pande, Hai Li, Krishnendu Chakrabarty. 1-7 [doi]
• Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary DataflowSungju Ryu, Youngtaek Oh, Jae-Joon Kim. 1-9 [doi]
• MinSC: An Exact Synthesis-Based Method for Minimal-Area Stochastic Circuits under Relaxed Error BoundXuan Wang, Zhufei Chu, Weikang Qian. 1-9 [doi]
• CORLD: In-Stream Correlation Manipulation for Low-Discrepancy Stochastic ComputingSina Asadi, M. Hassan Najafi, Mohsen Imani. 1-9 [doi]
• GraphLily: Accelerating Graph Linear Algebra on HBM-Equipped FPGAsYuwei Hu, Yixiao Du, Ecenur Ustun, Zhiru Zhang. 1-9 [doi]
• 2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited PaperYen-Chun Fang, Shao-Lun Huang, Chi-An Wu, Chung-Han Chou, Chih-Jen Hsu, WoeiTzy Jong, Kei-Yong Khoo. 1-6 [doi]
• METRICS2.1 and Flow Tuning in the IEEE CEDA Robust Design Flow and OpenROAD ICCAD Special Session PaperJinwook Jung, Andrew B. Kahng, Seungwon Kim, Ravi Varadarajan. 1-9 [doi]
• Design Space Exploration of Approximation-Based Quadruple Modular Redundancy CircuitsMarcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor. 1-9 [doi]
• Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog CircuitsArvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar. 1-9 [doi]
• Quarry: Quantization-based ADC Reduction for ReRAM-based Deep Neural Network AcceleratorsAzat Azamat, Faaiz Asim, Jongeun Lee. 1-7 [doi]
• ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTsSanmitra Banerjee, Arjun Chaudhuri, Jinwoo Kim, Gauthaman Murali, Mark Nelson, Sung Kyu Lim, Krishnendu Chakrabarty. 1-9 [doi]
• DALTA: A Decomposition-based Approximate Lookup Table ArchitectureChang Meng, Zhiyuan Xiang, Niyiqiu Liu, Yixuan Hu, Jiahao Song, Runsheng Wang, Ru Huang, Weikang Qian. 1-8 [doi]
• AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGATingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang 0012. 1-9 [doi]
• Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAsShiqing Li, Di Liu, Weichen Liu. 1-9 [doi]
• ICCAD Special Session Paper: Quantum Variational Methods for Quantum ApplicationsShouvanik Chakrabarti, Xuchen You, Xiaodi Wu. 1-7 [doi]
• Bit-Transformer: Transforming Bit-level Sparsity into Higher Preformance in ReRAM-based AcceleratorFangxin Liu, Wenbo Zhao, Zhezhi He, Zongwu Wang, Yilong Zhao, Yongbiao Chen, Li Jiang. 1-9 [doi]
• A Unified Framework for Layout Pattern Analysis with Deep Causal EstimationRan Chen, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Bei Yu, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao. 1-9 [doi]
• GPU Overdrive Fault Attacks on Neural NetworksMajid Sabbagh, Yunsi Fei, David R. Kaeli. 1-8 [doi]
• Contrastive Learning with Temporal Correlated Medical Images: A Case Study using Lung Segmentation in Chest X-Rays (Invited Paper)Dewen Zeng, John N. Kheir, Peng Zeng, Yiyu Shi. 1-7 [doi]
• Lower Voltage for Higher Security: Using Voltage Overscaling to Secure Deep Neural NetworksMd. Shohidul Islam, Ihsen Alouani, Khaled N. Khasawneh. 1-9 [doi]
• Rerec: In-ReRAM Acceleration with Access-Aware Mapping for Personalized RecommendationYitu Wang, Zhenhua Zhu, Fan Chen, Mingyuan Ma, Guohao Dai, Yu Wang, Hai Li, Yiran Chen. 1-9 [doi]
• Hotspot Detection via Multi-task Learning and Transformer EncoderBinwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng 0001, Bei Yu 0001, Martin D. F. Wong. 1-8 [doi]
• AdaCon: Adaptive Context-Aware Object Detection for Resource-Constrained Embedded DevicesMarina Neseem, Sherief Reda. 1-9 [doi]
• Algorithm and Hardware Co-design for Deep Learning-powered Channel Decoder: A Case StudyBoyang Zhang, Yang Sui, Lingyi Huang, Siyu Liao, Chunhua Deng, Bo Yuan 0001. 1-6 [doi]
• Toward Security Closure in the Face of Reliability Effects ICCAD Special Session PaperJens Lienig, Susann Rothe, Matthias Thiele, Nikhil Rangarajan, Mohammed Ashraf, Mohammed Nabeel, Hussam Amrouch, Ozgur Sinanoglu, Johann Knechtel. 1-9 [doi]
• Optimal Qubit Mapping with Simultaneous Gate Absorption ICCAD Special Session PaperBochen Tan, Jason Cong. 1-8 [doi]
• BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based MethodologyVidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar. 1-8 [doi]
• Split Compilation for Security of Quantum CircuitsAbdullah Ash-Saki, Aakarshitha Suresh, Rasit Onur Topaloglu, Swaroop Ghosh. 1-7 [doi]
• AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design FlowBulbul Ahmed, Fahim Rahman, Nick Hooten, Farimah Farahmandi, Mark M. Tehranipoor. 1-9 [doi]
• Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable NanotechnologiesAndreas Krinke, Shubham Rai, Akash Kumar 0001, Jens Lienig. 1-9 [doi]
• HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU ParallelismZizheng Guo, Tsung-Wei Huang, Yibo Lin. 1-9 [doi]
• 2021 ICCAD CAD Contest Problem B: Routing with Cell Movement Advanced: Invited PaperKai-Shun Hu, Tao-Chun Yu, Ming-Jen Yang, Cindy Chin-Fang Shen. 1-5 [doi]
• Improving the Robustness of Redundant Execution with Register File RandomizationIlya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López 0001, Jose Flich, Carles Hernández. 1-9 [doi]
• Doomed Run Prediction in Physical Design by Exploiting Sequential Flow and Graph LearningYi-Chen Lu, Siddhartha Nath, Vishal Khandelwal, Sung Kyu Lim. 1-9 [doi]
• Exploration of Quantum Neural Architecture by Mixing Quantum Neuron Designs: (Invited Paper)Zhepeng Wang, Zhiding Liang, Shanglin Zhou, Caiwen Ding, Yiyu Shi, Weiwen Jiang. 1-7 [doi]
• When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised LearningHao Geng, Fan Yang, Xuan Zeng 0001, Bei Yu 0001. 1-8 [doi]
• Circuit Deobfuscation from Power Side-Channels using Pseudo-Boolean SATKaveh Shamsi, Yier Jin. 1-9 [doi]
• FedSwap: A Federated Learning based 5G Decentralized Dynamic Spectrum Access SystemZhihui Gao, Ang Li, Yunfan Gao, Bing Li, Yu Wang, Yiran Chen. 1-6 [doi]
• Exploring eFPGA-based Redaction for IP ProtectionJitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan 0001, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri. 1-9 [doi]
• Bounded Model Checking of Speculative Non-InterferenceEmmanuel Pescosta, Georg Weissenbacher, Florian Zuleger. 1-9 [doi]
• DATC RDF-2021: Design Flow and Beyond ICCAD Special Session PaperJianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Victor N. Kravets, Yih-Lang Li, Ravi Varadarajan, Mingyu Woo. 1-6 [doi]
• Deferred Dropout: An Algorithm-Hardware Co-Design DNN Training Method Provisioning Consistent High Activation SparsityKangKyu Park, Yunki Han, Lee-Sup Kim. 1-9 [doi]
• Acceleration Method for Learning Fine-Layered Optical Neural NetworksKazuo Aoyama, Hiroshi Sawada. 1-9 [doi]
• SSR: A Skeleton-based Synthesis Flow for Hybrid Processing-in-RRAM ModesFeng Wang, Guangyu Sun 0003, Guojie Luo. 1-9 [doi]
• DevelSet: Deep Neural Level Set for Instant Mask OptimizationGuojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, Bei Yu 0001. 1-9 [doi]
• An Efficient Two-phase Method for Prime Compilation of Non-clausal Boolean FormulaeWeilin Luo, Hai Wan, Hongzhen Zhong, Ou Wei, Biqing Fang, Xiaotong Song. 1-9 [doi]
• Federated Contrastive Learning for Dermatological Disease Diagnosis via On-device Learning (Invited Paper)Yawen Wu, Dewen Zeng, Zhepeng Wang, Yi-sheng, Lei Yang, Alaina J. James, Yiyu Shi, Jingtong Hu. 1-7 [doi]
• OpenSAR: An Open Source Automated End-to-end SAR ADC CompilerMingjie Liu, Xiyuan Tang, Keren Zhu 0001, Hao Chen, Nan Sun, David Z. Pan. 1-9 [doi]
• From Specification to Topology: Automatic Power Converter Design via Reinforcement LearningShaoze Fan, Ningyuan Cao, Shun Zhang, Jing Li, Xiaoxiao Guo, Xin Zhang. 1-9 [doi]
• Simultaneous Transistor Folding and Placement in Standard Cell Layout SynthesisKyeonghyeon Baek, Taewhan Kim. 1-8 [doi]
• Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State CompressionCheng Zeng, Fan Yang, Xuan Zeng 0001. 1-8 [doi]
• A High-Performance Accelerator for Super-Resolution Processing on Embedded GPUWenqian Zhao, Qi Sun, Yang Bai, Wenbo Li, Haisheng Zheng, Bei Yu 0001, Martin D. F. Wong. 1-9 [doi]
• Security Closure of Physical Layouts ICCAD Special Session PaperJohann Knechtel, Jayanth Gopinath, Jitendra Bhandari, Mohammed Ashraf, Hussam Amrouch, Shekhar Borkar, Sung Kyu Lim, Ozgur Sinanoglu, Ramesh Karri. 1-9 [doi]
• Analytical Modeling of Transient Electromigration Stress based on Boundary ReflectionsMohammad Abdullah Al Shohel, Vidya A. Chhabria, Nestor E. Evmorfopoulos, Sachin S. Sapatnekar. 1-8 [doi]
• Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework ICCAD Special Session PaperMuhammad Shafique 0001, Alberto Marchisio, Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif. 1-9 [doi]
• ToPro: A Topology Projector and Waveguide Router for Wavelength-Routed Optical Networks-on-ChipZhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. 1-9 [doi]
• Relative-Scheduling-Based High-Level Synthesis for Flow-Based Microfluidic BiochipsFangda Zuo, Mengchu Li, Tsun-Ming Tseng, Tsung-Yi Ho, Ulf Schlichtmann. 1-9 [doi]
• Banshee: A Fast LLVM-Based RISC-V Binary TranslatorSamuel Riedel, Fabian Schuiki, Paul Scheffler, Florian Zaruba, Luca Benini. 1-9 [doi]
• Heuristics for Million-scale Two-level Logic MinimizationMahdi Nazemi, Hitarth Kanakia, Massoud Pedram. 1-7 [doi]
• A General Hardware and Software Co-Design Framework for Energy-Efficient Edge AINitthilan Kannappan Jayakodi, Janardhan Rao Doppa, Partha Pratim Pande. 1-7 [doi]
• Stealing Neural Network Models through the Scan Chain: A New Threat for ML HardwareSeetal Potluri, Aydin Aysu. 1-8 [doi]
• Robust Time-Sensitive Networking with Delay Bound AnalysesGuoqi Xie, Xiangzhen Xiao, Hong Liu, Renfa Li, Wanli Chang 0001. 1-9 [doi]
• BigIntegr: One-Pass Architectural Synthesis for Continuous-Flow Microfluidic Lab-on-a-Chip SystemsXing Huang, Youlin Pan, Zhen Chen, Wenzhong Guo, Robert Wille, Tsung-Yi Ho, Ulf Schlichtmann. 1-8 [doi]
• 2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic RewritingGhasem Pasandi, Sreedhar Pratty, David Brown, Yanqing Zhang, Haoxing Ren, Brucek Khailany. 1-6 [doi]
• Can Noise on Qubits Be Learned in Quantum Neural Network? A Case Study on QuantumFlow (Invited Paper)Zhiding Liang, Zhepeng Wang, Junhuan Yang, Lei Yang, Yiyu Shi, Weiwen Jiang. 1-7 [doi]
• Optimizing FPGA-based Accelerator Design for Large-Scale Molecular Similarity Search (Special Session Paper)Hongwu Peng, Shiyang Chen, Zhepeng Wang, Junhuan Yang, Scott A. Weitze, Tong Geng, Ang Li, Jinbo Bi, Minghu Song, Weiwen Jiang, Hang Liu, Caiwen Ding. 1-7 [doi]
• An OCV-Aware Clock Tree Synthesis MethodologyNecati Uysal, Rickard Ewetz. 1-9 [doi]
• Compatible Equivalence Checking of X-Valued CircuitsYu-Neng Wang, Yun-Rong Luo, Po-Chun Chien, Ping-Lun Wang, Hao-Ren Wang, Wan-Hsuan Lin, Jie-Hong Roland Jiang, Chung-Yang (Ric) Huang. 1-9 [doi]
• Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPsMehran Goli, Rolf Drechsler. 1-8 [doi]
• ReSpawn: Energy-Efficient Fault-Tolerance for Spiking Neural Networks considering Unreliable MemoriesRachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 1-9 [doi]
• A Row-Based Algorithm for Non-Integer Multiple-Cell-Height PlacementZih-Yao Lin, Yao-Wen Chang. 1-6 [doi]
• DeepFreeze: Cold Boot Attacks and High Fidelity Model Recovery on Commercial EdgeML DeviceYoo-Seung Won, Soham Chatterjee, Dirmanto Jap, Arindam Basu, Shivam Bhasin. 1-9 [doi]
• Feedback-Guided Circuit Structure Mutation for Testing Hardware Model CheckersChengyu Zhang 0001, Minquan Sun, Jianwen Li, Ting Su 0001, Geguang Pu. 1-9 [doi]
• DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural NetworksAqeeb Iqbal Arka, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. 1-9 [doi]
• Hybrid Analog-Digital In-Memory ComputingMuhammad Rashedul Haq Rashed, Sumit Kumar Jha 0001, Rickard Ewetz. 1-9 [doi]
• Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI DesignsJai-Ming Lin, Chung-Wei Huang, Liang-Chi Zane, Min-Chia Tsai, Che-Li Lin, Chen-Fa Tsai. 1-8 [doi]
• Manufacturing Cycle-Time Optimization Using Gaussian Drying Model for Inkjet-Printed ElectronicsTsun-Ming Tseng, Meng Lian, Mengchu Li, Philipp Rinklin, Leroy Grob, Bernhard Wolfrum, Ulf Schlichtmann. 1-8 [doi]
• Massively Parallel Big Data Classification on a Programmable Processing In-Memory ArchitectureYeseong Kim, Mohsen Imani, Saransh Gupta, Minxuan Zhou, Tajana Simunic Rosing. 1-9 [doi]
• Engineering an Efficient Boolean Functional Synthesis EnginePriyanka Golia, Friedrich Slivovsky, Subhajit Roy, Kuldeep S. Meel. 1-9 [doi]
• ScaleDNN: Data Movement Aware DNN Training on Multi-GPUWeizheng Xu, Ashutosh Pattnaik, Geng Yuan, Yanzhi Wang, Youtao Zhang, Xulong Tang. 1-9 [doi]
• Accelerating Framework of Transformer by Hardware Design and Model Compression Co-OptimizationPanjie Qi, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Hongwu Peng, Shaoyi Huang, Zhenglun Kong, Yuhong Song, Bingbing Li. 1-9 [doi]
• CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Full-Chip Parasitic ExtractionDingcheng Yang, Wenjian Yu, Yuanbo Guo, Wenjie Liang. 1-9 [doi]
• HASHTAG: Hash Signatures for Online Detection of Fault-Injection Attacks on Deep Neural NetworksMojan Javaheripi, Farinaz Koushanfar. 1-9 [doi]
• Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning ApproachWei Zeng 0015, Azadeh Davoodi, Rasit Onur Topaloglu. 1-9 [doi]
• Demystifying the Characteristics of High Bandwidth Memory for Real-Time SystemsKazi Asifuzzaman, Mohamed Abuelala, Mohamed Hassan, Francisco J. Cazorla. 1-9 [doi]
• Generalizable Cross-Graph Embedding for GNN-based Congestion PredictionAmur Ghose, Vincent Zhang, Yingxue Zhang, Dong Li, Wulong Liu, Mark Coates. 1-9 [doi]
• A Design Flow for Mapping Spiking Neural Networks to Many-Core Neuromorphic HardwareShihao Song, M. Lakshmi Varshika, Anup Das 0001, Nagarajan Kandasamy. 1-9 [doi]
• Brain-Inspired Computing: Adventure from Beyond CMOS Technologies to Beyond von Neumann Architectures ICCAD Special Session PaperHussam Amrouch, Jian-Jia Chen, Kaushik Roy 0001, Yuan Xie 0001, Indranil Chakraborty, Wenqin Huangfu, Ling Liang, Fengbin Tu, Cheng Wang, Mikail Yayla. 1-9 [doi]
• FlowTuner: A Multi-Stage EDA Flow Tuner Exploiting Parameter Knowledge TransferRongjian Liang, Jinwook Jung, Hua Xiang, Lakshmi N. Reddy, Alexey Lvov, Jiang Hu, Gi-Joon Nam. 1-9 [doi]
• Quantum Machine Learning for Finance ICCAD Special Session PaperMarco Pistoia, Syed Farhan Ahmad, Akshay Ajagekar, Alexander Buts, Shouvanik Chakrabarti, Dylan Herman, Shaohan Hu, Andrew Jena, Pierre Minssen, Pradeep Niroula, Arthur G. Rattew, Yue Sun, Romina Yalovetzky. 1-9 [doi]
• Online and Offline Machine Learning for Industrial Design Flow Tuning: (Invited - ICCAD Special Session Paper)Matthew M. Ziegler, Jihye Kwon, Hung-Yi Liu, Luca P. Carloni. 1-9 [doi]
• Quantum-Classical Hybrid Machine Learning for Image Classification (ICCAD Special Session Paper)Mahabubul Alam, Satwik Kundu, Rasit Onur Topaloglu, Swaroop Ghosh. 1-7 [doi]
• RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number SystemsArman Roohi, MohammadReza Taheri, Shaahin Angizi, Deliang Fan. 1-9 [doi]
• GPU-accelerated Critical Path Generation with Path ConstraintsGuannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong. 1-9 [doi]
• Fast and Accurate PPA Modeling with Transfer LearningW. Rhett Davis, Paul D. Franzon, Luis Francisco, Billy Huggins, Rajeev Jain. 1-8 [doi]
• Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAsDajiang Liu, Ting Liu, Xingyu Mo, Jiaxing Shang, Shouyi Yin. 1-9 [doi]
• Graph Learning-Based Arithmetic Block IdentificationZhuolun He, Ziyi Wang, Chen Bail, Haoyu Yang, Bei Yu. 1-8 [doi]
• Time-Division Multiplexing Based System-Level FPGA RoutingWei-Kai Liu, Ming-Hung Chen, Chia-Ming Chang, Chen-Chia Chang, Yao-Wen Chang. 1-6 [doi]
• From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer LearningJuzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen. 1-9 [doi]
• McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUsJianwang Zhai, Chen Bai, Binwu Zhu, Yici Cai, Qiang Zhou 0001, Bei Yu 0001. 1-9 [doi]
• On-chip Optical Routing with Waveguide Matching ConstraintsFu-Yu Chuang, Yao-Wen Chang. 1-6 [doi]
• G-CoS: GNN-Accelerator Co-Search Towards Both Better Accuracy and EfficiencyYongan Zhang, Haoran You, Yonggan Fu, Tong Geng, Ang Li, Yingyan Lin. 1-9 [doi]
• Automatic Routability Predictor Development Using Neural Architecture SearchChen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen. 1-9 [doi]
• Overview of 2021 CAD Contest at ICCADTsung-Wei Huang, Yu-Guang Chen, Chun-Yao Wang, Takashi Sato. 1-3 [doi]
• O-HAS: Optical Hardware Accelerator Search for Boosting Both Acceleration Performance and Development SpeedMengquan Li, Zhongzhi Yu, Yongan Zhang, Yonggan Fu, Yingyan Lin. 1-9 [doi]
• dCSR: A Memory-Efficient Sparse Matrix Representation for Parallel Neural Network InferenceElias Trommer, Bernd Waschneck, Akash Kumar 0001. 1-9 [doi]
• Starfish: An Efficient P&R Co-Optimization Engine with A*-based Partial ReroutingFangzhou Wang, Lixin Liu, Jingsong Chen, Jinwei Liu, Xinshi Zang, Martin D. F. Wong. 1-9 [doi]
• Reliable Memristor-based Neuromorphic Design Using Variation- and Defect-Aware TrainingDi Gaol, Grace Li Zhang, Xunzhao Yin, Bing Li, Ulf Schlichtmann, Cheng Zhuo. 1-9 [doi]
• Overcoming the Memory Hierarchy Inefficiencies in Graph Processing ApplicationsJilan Lin, Shuangchen Li, Yufei Ding, Yuan Xie 0001. 1-9 [doi]
• 2: Morphable Encryption and Encoding for Secure NVMWei Zhao, Dan Feng, Yu Hua0001, Wei Tong 0001, Jingning Liu, Jie Xu 0013, Chunyan Li, Gaoxiang Xu, Yiran Chen. 1-8 [doi]
• Crossbar based Processing in Memory Accelerator Architecture for Graph Convolutional NetworksNagadastagiri Challapalle, Karthik Swaminathan, Nandhini Chandramoorthy, Vijaykrishnan Narayanan. 1-9 [doi]
• VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware SynthesisHadi Esmaeilzadeh, Soroush Ghodrati, Jie Gu 0003, Shiyu Guo, Andrew B. Kahng, Joon Kyung Kim, Sean Kinzer, Rohan Mahapatra, Susmita Dey Manasi, Edwin Mascarenhas, Sachin S. Sapatnekar, Ravi Varadarajan, Zhiang Wang, Hanyang Xu, Brahmendra Reddy Yatham, Ziqing Zeng. 1-7 [doi]
• ICCAD Tutorial Session Paper Ferroelectric FET Technology and Applications: From Devices to SystemsHussam Amrouch, Di Gao, Xiaobo Sharon Hu, Arman Kazemi, Ann Franchesca Laguna, Kai Ni 0004, Michael T. Niemier, Mohammad Mehdi Sharifi, Simon Thomann, Xunzhao Yin, Cheng Zhuo. 1-8 [doi]
• LayerPipe: Accelerating Deep Neural Network Training by Intra-Layer and Inter-Layer Gradient Pipelining and Multiprocessor SchedulingNanda K. Unnikrishnan, Keshab K. Parhi. 1-8 [doi]
• TopoPart: a Multi-level Topology-Driven Partitioning Framework for Multi-FPGA SystemsDan Zheng, Xinshi Zang, Martin D. F. Wong. 1-8 [doi]
• ReIGNN: State Register Identification Using Graph Neural Networks for Circuit Reverse EngineeringSubhajit Dutta Chowdhury, Kaixin Yang, Pierluigi Nuzzo. 1-9 [doi]
• Improving Inter-kernel Data Reuse With CTA-Page Coordination in GPGPUXuanyi Li, Chen Li 0015, Yang Guo 0003, Rachata Ausavarungnirun. 1-9 [doi]
• DAPA: A Dataflow-Aware Analytical Placement Algorithm for Modern Mixed-Size Circuit DesignsJai-Ming Lin, Wei-Fan Huang, Yao-Chieh Chen, Yi-ting Wang, Po-Wen Wang. 1-8 [doi]
• A Circuit-Based SAT Solver for Logic SynthesisHe-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko. 1-6 [doi]
• Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic NoiseXiaoxuan Yang, Syrine Belakaria, Biresh Kumar Joardar, Huanrui Yang, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty, Hai Helen Li. 1-9 [doi]
• An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient CircuitsHao Zhang, Weifeng He, Yanan Sun 0003, Mingoo Seok. 1-9 [doi]
• GAMER: GPU Accelerated Maze RoutingShiju Lin, Jinwei Liu, Martin D. F. Wong. 1-8 [doi]
• Traffic-Adaptive Power Reconfiguration for Energy-Efficient and Energy-Proportional Optical InterconnectsYuyang Wang, Kwang-Ting Cheng. 1-9 [doi]
• Positive/Negative Approximate Multipliers for DNN AcceleratorsOurania Spantidi, Georgios Zervakis, Iraklis Anagnostopoulos, Hussam Amrouch, Jörg Henkel. 1-9 [doi]
• Enhanced Fast Boolean Matching based on Sensitivity Signatures PruningJiaxi Zhang 0001, Liwei Ni, Shenggen Zheng, Hao Liu, Xiangfu Zou, Feng Wang, Guojie Luo. 1-9 [doi]
• AutoGTCO: Graph and Tensor Co-Optimize for Image Recognition with Transformers on GPUYang Bai, Xufeng Yao, Qi Sun, Bei Yu 0001. 1-9 [doi]
• A Convergence Monitoring Method for DNN Training of On-Device Task AdaptationSeungkyu Choi, Jaekang Shin, Lee-Sup Kim. 1-9 [doi]
• Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNsElbruz Ozen, Alex Orailoglu. 1-8 [doi]
• Binarized SNNs: Efficient and Error-Resilient Spiking Neural Networks through BinarizationMing-Liang Wei, Mikail Yayla, Shu-Yin Ho, Jian-Jia Chen, Chia-Lin Yang, Hussam Amrouch. 1-9 [doi]
• Hierarchical Layout Synthesis and Optimization Framework for High-Density Power Module Design AutomationImam Al Razi, Quang Le, H. Alan Mantooth, Yarui Peng. 1-8 [doi]
• BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration FrameworkChen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong. 1-9 [doi]
• iSTELLAR: intermittent Signature aTtenuation Embedded CRYPTO with Low-Level metAl RoutingJeremy Blackstone, Debayan Das, Alric Althoff, Shreyas Sen, Ryan Kastner. 1-9 [doi]
• Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning AcceleratorsSerena Curzel, Nicolas Bohm Agostini, Shihao Song, Ismet Dagli, Ankur Limaye, Cheng Tan 0001, Marco Minutoli, Vito Giovanni Castellana, Vinay Amatya, Joseph B. Manzano, Anup Das 0001, Fabrizio Ferrandi, Antonino Tumeo. 1-7 [doi]
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