Abstract is missing.
- Estimating the Limits of CPU Power Management for Mobile GamesBenedikt Dietrich, Nadja Peters, Sangyoung Park, Samarjit Chakraborty. 1-8 [doi]
- BioChipWork: Reverse Engineering of Microfluidic BiochipsHuili Chen, Seetal Potluri, Farinaz Koushanfar. 9-16 [doi]
- Subcomponent Timing-Based Detection of Malware in Embedded SystemsSixing Lu, Roman Lysecky, Jerzy W. Rozenblit. 17-24 [doi]
- Security Trade-Offs in Microfluidic Routing FabricsJack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri. 25-32 [doi]
- Side-Channel Attack on STTRAM Based Cache for Cryptographic ApplicationMohammad Nasim Imtiaz Khan, Shivam Bhasin, Alex Yuan, Anupam Chattopadhyay, Swaroop Ghosh. 33-40 [doi]
- Template Attack Based Deobfuscation of Integrated CircuitsAbhishek Chakraborty, Yang Xie, Ankur Srivastava. 41-44 [doi]
- Neural TrojansYuntao Liu, Yang Xie, Ankur Srivastava. 45-48 [doi]
- Adaptive Prefetching for Accelerating Read and Write in NVM-Based File SystemsShengan Zheng, Hong Mei, Linpeng Huang, Yanyan Shen, Yanmin Zhu. 49-56 [doi]
- A Cost-Efficient NVM-Based Journaling Scheme for File SystemsXiaoyi Zhang, Dan Feng, Yu Hua, Jianxi Chen. 57-64 [doi]
- TDV Cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion PerspectiveTianyue Lu, Yuhang Liu, Haiyang Pan, Mingyu Chen. 65-72 [doi]
- RCTP: Region Correlated Temporal PrefetcherDennis Antony Varkey, Biswabandan Panda, Madhu Mutyam. 73-80 [doi]
- A Shingle-Aware Persistent Cache Management Scheme for DM-SMR DisksTianming Yang, Haitao Wu, Ping Huang, Fei Zhang. 81-88 [doi]
- Low-Power and High-Speed Approximate Multiplier Design with a Tree CompressorTongxin Yang, Tomoaki Ukezono, Toshinori Sato. 89-96 [doi]
- Neural Network Classifiers Using Stochastic Computing with a Hardware-Oriented Approximate Activation FunctionBingzhe Li, Yaobin Qin, Bo Yuan, David J. Lilja. 97-104 [doi]
- Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural NetworksJoonsang Yu, Kyounghoon Kim, Jongeun Lee, Kiyoung Choi. 105-112 [doi]
- Approximate Reconfigurable Hardware Accelerator: Adapting the Micro-Architecture to Dynamic WorkloadsSiyuan Xu, Benjamin Carrión Schäfer. 113-120 [doi]
- Low Latency Approximate Adder for Highly Correlated Input StreamsXiaoliang Chen, Ahmed M. Eltawil, Fadi J. Kurdahi. 121-124 [doi]
- Power and Area Efficient Sorting Networks Using Unary ProcessingM. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan. 125-128 [doi]
- Machine Learning-Based Approaches for Energy-Efficiency Prediction and Scheduling in Composite Cores ArchitecturesHossein Sayadi, Nisarg Patel, Avesta Sasan, Houman Homayoun. 129-136 [doi]
- LACore: A Supercomputing-Like Linear Algebra Accelerator for SoC-Based DesignsSamuel Steffl, Sherief Reda. 137-144 [doi]
- H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core ProcessorVinesh Srinivasan, Rangeen Basu Roy Chowdhury, Elliott Forbes, Randy Widialaksono, Zhenqian Zhang, Joshua Schabel, Sungkwan Ku, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon. 145-152 [doi]
- ABDTR: Approximation-Based Dynamic Traffic Regulation for Networks-on-Chip SystemsLing Wang, Xiaohang Wang, Yadong Wang. 153-160 [doi]
- CAGE: A Contention-Aware Game-Theoretic Model for Heterogeneous Resource AssignmentDiman Zad Tootaghaj, Farshid Farhat. 161-164 [doi]
- Energy-Aware Task Scheduling on Heterogeneous NoC-Based MPSoCsSuhaimi Abd Ishak, Hui Wu, Umair Ullah Tariq. 165-168 [doi]
- Effective Signal Restoration in Post-Silicon ValidationXiaobang Liu, Ranga Vemuri. 169-176 [doi]
- A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol DebugYuting Cao, Hao Zheng, Hernan M. Palombo, Sandip Ray, Jin Yang. 177-184 [doi]
- QUEBS: Qualifying Event Based Search in Concolic Testing for Validation of RTL ModelsAlif Ahmed, Prabhat Mishra. 185-192 [doi]
- Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis ReductionFarimah Farahmandi, Prabhat Mishra. 193-200 [doi]
- GraphTuner: An Input Dependence Aware Loop Perforation Scheme for Efficient Execution of Approximated Graph AlgorithmsHamza Omar, Masab Ahmad, Omer Khan. 201-208 [doi]
- A High-Performance Deeply Pipelined Architecture for Elementary Transcendental Function EvaluationJing Chen, Xue Liu. 209-216 [doi]
- Congra: Towards Efficient Processing of Concurrent Graph Queries on Shared-Memory MachinesPeitian Pan, Chao Li. 217-224 [doi]
- Exploring Scalable Data Allocation and Parallel Computing on NoC-Based Embedded Many CoresYuya Maruyama, Shinpei Kato, Takuya Azumi. 225-228 [doi]
- DAS: An Efficient NoC Router for Mixed-Criticality Real-Time SystemsMourad Dridi, Stéphane Rubini, Mounir Lallali, Martha Johanna Sepúlveda Flórez, Frank Singhoff, Jean-Philippe Diguet. 229-232 [doi]
- Monolithic 3D-Enabled High Performance and Energy Efficient Network-on-ChipSourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. 233-240 [doi]
- Vulnerability-Aware Energy Optimization Using Reconfigurable Caches in Multicore SystemsYuanwen Huang, Prabhat Mishra. 241-248 [doi]
- Dependency-Aware Parallel Routing for Large-Scale FPGAsMinghua Shen, Nong Xiao, Guojie Luo. 249-256 [doi]
- Design Exploration for Multiple Level Cell Based Non-Volatile FPGAsKe Liu, Mengying Zhao, Lei Ju, Zhiping Jia, Chun Jason Xue, Jingtong Hu. 257-264 [doi]
- LDPC-Based Adaptive Multi-Error Correction for 3D MemoriesMihai Lefter, George Razvan Voicu, Thomas Marconi, Valentin Savin, Sorin Dan Cotofana. 265-268 [doi]
- ILP-Based Identification of Redundant Logic Insertions for Opportunistic Yield Improvement during Early Process LearningTuck Boon Chan, Wei-Ting Jonas Chan, Andrew B. Kahng. 269-272 [doi]
- A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge ComputingChi Lo, Yu-Yi Su, Chun-Yi Lee, Shih-Chieh Chang. 273-280 [doi]
- DAWS: Exploiting Crossbar Characteristics for Improving Write Performance of High Density Resistive MemoryChengning Wang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu, Yang Zhang. 281-288 [doi]
- Hardware Acceleration of Bayesian Neural Networks Using RAM Based Linear Feedback Gaussian Random Number GeneratorsRuizhe Cai, Ao Ren, Luhao Wang, Massoud Pedram, Yanzhi Wang. 289-296 [doi]
- Low Power Spatial Localization of Mobile Sensors with Recurrent Neural NetworkNick Iliev, Amit Ranjan Trivedi. 297-300 [doi]
- An FPGA-Based Coprocessor for Hash Unit AccelerationAbbas Fairouz, Sunil P. Khatri. 301-304 [doi]
- Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel AttackChenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang. 305-312 [doi]
- FSM Anomaly Detection Using Formal AnalysisFarimah Farahmandi, Prabhat Mishra. 313-320 [doi]
- Automatic Security Property Generation for Detecting Information-Leaking Hardware TrojansChenguang Wang, Yici Cai, Qiang Zhou. 321-328 [doi]
- Implications of Distributed On-Chip Power Delivery on EM Side-Channel AttacksAhmed Waheed Khan, Tanya Wanchoo, Gokhan Mumcu, Selçuk Köse. 329-336 [doi]
- Fingerprinting Field Programmable Gate ArraysVinayaka Jyothi, Ashik Poojari, Richard Stern, Ramesh Karri. 337-340 [doi]
- Logic Obfuscation against IC Reverse Engineering Attacks Using PLGsQutaiba Alasad, Jiann Yuan. 341-344 [doi]
- DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance CachingNewton, Sujit Kr Mahto, Suhit Pai, Virendra Singh. 345-352 [doi]
- Dual Dictionary Compression for the Last Level CacheAkshay Lahiry, David Kaeli. 353-360 [doi]
- Jenga: Efficient Fault Tolerance for Stacked DRAMGeorgios Mappouras, Alireza Vahid, A. Robert Calderbank, Derek R. Hower, Daniel J. Sorin. 361-368 [doi]
- SelSMaP: A Selective Stride Masking Prefetching SchemeJiajun Wang, Reena Panda, Lizy Kurian John. 369-372 [doi]
- T2: A Highly Accurate and Energy Efficient Stride PrefetcherSushant Kondguli, Michael Huang. 373-376 [doi]
- Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed AutomataMehran Goli, Jannis Stoppe, Rolf Drechsler. 377-384 [doi]
- Crosstalk Free Coding Systems to Protect NoC Channels against Crosstalk FaultsKimia Soleimani, Ahmad Patooghy, Nasim Soltani, Lake Bu, Michel A. Kinsy. 385-390 [doi]
- Limited Magnitude Error Correction Using OLS Codes for Memories with Multilevel CellsAbhishek Das, Nur A. Touba. 391-394 [doi]
- Yoda: Judge Me by My Size, Do You?Jiangwei Zhang, Donald Kline Jr., Liang Fang, Rami G. Melhem, Alex K. Jones. 395-398 [doi]
- Fast Search-Based RTL Test Generation Using Control-Flow Path GuidanceSonal Pinto, Michael S. Hsiao. 399-402 [doi]
- DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm NodeJiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan. 403-410 [doi]
- Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam LithographySudipta Paul, Pritha Banerjee, Susmita Sur-Kolay. 411-414 [doi]
- Patterning Aware Design Optimization of Selective Etching in N5 and BeyondYibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan. 415-418 [doi]
- Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable LogicMichaela Blott, Thomas B. Preuber, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser. 419-422 [doi]
- The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud SystemsLorenzo Di Tucci, Marco Rabozzi, Luca Stornaiuolo, Marco D. Santambrogio. 423-426 [doi]
- A Common Backend for Hardware Acceleration on FPGAEmanuele Del Sozzo, Riyadh Baghdadi, Saman Amarasinghe, Marco D. Santambrogio. 427-430 [doi]
- Towards Accelerating Generic Machine Learning Prediction PipelinesAlberto Scolari, Yunseong Lee, Markus Weimer, Matteo Interlandi. 431-434 [doi]
- Convolutional Neural Networks on Dataflow EnginesNils Voss, Marco Bacis, Oskar Mencer, Georgi Gaydadjiev, Wayne Luk. 435-438 [doi]
- Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge ExtractionZhezhi He, Shaahin Angizi, Deliang Fan. 439-446 [doi]
- Floating Point Square Root under HUB FormatJulio Villalba-Moreno, Javier Hormigo. 447-454 [doi]
- Read Error Resilient MLC STT-MRAM Based Last Level CacheWen Wen, Youtao Zhang, Jun Yang. 455-462 [doi]
- Ultra-Fast SOT-MRAM Cell with STT Current for Deterministic SwitchingBehzad Zeinali, Jens Kargaard Madsen, Praveen Raghavan, Farshad Moradi. 463-468 [doi]
- Pulse Ring Oscillator Tuning via Pulse DynamicsAditya Dalakoti, Merritt Miller, Forrest Brewer. 469-472 [doi]
- DLL-Assisted Clock Synchronization Method for Multi-Die ICsChia-Yuan Cheng, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou. 473-476 [doi]
- M2S-CGM: A Detailed Architectural Simulator for Coherent CPU-GPU SystemsChristopher E. Giles, Mark A. Heinrich. 477-484 [doi]
- Sharing-Aware Efficient Private Caching in Many-Core Server ProcessorsSudhanshu Shukla, Mainak Chaudhuri. 485-492 [doi]
- Decomposed Task Mapping to Maximize QoS in Energy-Constrained Real-Time MulticoresLei Mo, Angeliki Kritikakou, Olivier Sentieys. 493-500 [doi]
- Using Application-Level Thread Progress Information to Manage Power and PerformanceSabrina M. Neuman, Jason E. Miller, Daniel Sánchez 0003, Srinivas Devadas. 501-508 [doi]
- Configurable SoC In-Situ Hardware/Software Co-Design Design Space ExplorationSiyuan Xu, Benjamin Carrión Schäfer, Yidi Liu. 509-512 [doi]
- Quality of Service-Aware Dynamic Voltage and Frequency Scaling for Mobile 3D Graphics ApplicationsNavid Farazmand, David R. Kaeli. 513-516 [doi]
- Approximate Disjoint Bi-Decomposition and Its Application to Approximate Logic SynthesisYue Yao, Shuyang Huang, Chen Wang, Yi Wu, Weikang Qian. 517-524 [doi]
- Timing-Abstract Circuit Design in Transaction-Level VerilogSteven F. Hoover. 525-532 [doi]
- ReHLS: Resource-Aware Program Transformation Workflow for High-Level SynthesisAtieh Lotfi, Rajesh K. Gupta. 533-536 [doi]
- Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy AttacksSamah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Robert Wille, Ramesh Karri. 537-540 [doi]
- Compiler-Assisted Threshold Implementation against Power Analysis AttacksPei Luo, Konstantinos Athanasiou, Liwei Zhang, Zhen Hang Jiang, Yunsi Fei, A. Adam Ding, Thomas Wahl. 541-544 [doi]
- TAINT: Tool for Automated INsertion of TrojansVinayaka Jyothi, Prashanth Krishnamurthy, Farshad Khorrami, Ramesh Karri. 545-548 [doi]
- A Scale-Out Enterprise Storage ArchitectureWonil Choi, Myoungsoo Jung, Mahmut T. Kandemir, Chita R. Das. 549-556 [doi]
- CloudShelter: Protecting Virtual Machines' Memory Resource Availability in CloudsTianwei Zhang, Yuan Xu, Yungang Bao, Ruby B. Lee. 557-564 [doi]
- Using Disturbance Compensation and Data Clustering (DC)2 to Improve Reliability and Performance of 3D MLC Flash MemoryYazhi Feng, Dan Feng, Wei Tong, Yu Jiang, Chuanqi Liu. 565-572 [doi]
- Improving Performance of TLC RRAM with Compression-Ratio-Aware Data EncodingJie Xu, Dan Feng, Yu Hua, Wei Tong, Jingning Liu, Chunyan Li, Wen Zhou. 573-580 [doi]
- Encoding Separately: An Energy-Efficient Write Scheme for MLC STT-RAMJie Xu, Dan Feng, Wei Tong, Jingning Liu, Wen Zhou. 581-584 [doi]
- Quick-and-Dirty: Improving Performance of MLC PCM by Using Temporary Short WritesMingzhe Zhang, Lunkai Zhang, Lei Jiang, Frederic T. Chong, Zhiyong Liu. 585-588 [doi]
- Applications of Deep Neural Networks for Ultra Low Power IoTSreela Kodali, Patrick Hansen, Niamh Mulholland, Paul N. Whatmough, David M. Brooks, Gu-Yeon Wei. 589-592 [doi]
- Cross-Layer Resilience in Low-Voltage Digital Systems: Key InsightsEric Cheng, Jacob A. Abraham, Pradip Bose, Alper Buyuktosunoglu, Keith A. Campbell, Deming Chen, Chen-Yong Cher, Hyungmin Cho, Binh Le, Klas Lilja, Shahrzad Mirkhani, Kevin Skadron, Mircea Stan, Lukasz G. Szafaryn, Christos Vezyrtzis, Subhasish Mitra. 593-596 [doi]
- Pre-RTL Voltage and Power Optimization for Low-Cost, Thermally Challenged Multicore ChipsAlec Roelke, Runjie Zhang, Kaushik Mazumdar, Ke Wang, Kevin Skadron, Mircea R. Stan. 597-600 [doi]
- Very Low Voltage (VLV) DesignRamon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler. 601-604 [doi]
- Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial OptimizationYong Shim, Akhilesh Jaiswal, Kaushik Roy 0001. 605-608 [doi]
- Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAMDeliang Fan, Shaahin Angizi. 609-612 [doi]
- Programmable Stateful In-Memory Computing Paradigm via a Single Resistive DeviceWang Kang, He Zhang, Peng Ouyang, Youguang Zhang, Weisheng Zhao. 613-616 [doi]
- NUPLet: A Photonic Based Multi-Chip NUCA ArchitectureJanibul Bashir, Smruti R. Sarangi. 617-624 [doi]
- RAPS: Restore-Aware Policy Selection for STT-MRAM-Based Main Memory under Read DisturbanceArmin Haj Aboutalebi, Lide Duan. 625-632 [doi]
- BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU WorkloadsYuxi Liu, Xia Zhao, Zhibin Yu, Zhenlin Wang, Xiaolin Wang, Yingwei Luo, Lieven Eeckhout. 633-640 [doi]
- Efficient Tagged MemoryAlexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W. Moore, Alex Bradbury, Hongyan Xia, Robert N. M. Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey D. Son, A. Theodore Markettos. 641-648 [doi]
- Improving Execution Time of Parallel Programs on Large Scale Chip Multiprocessors with Constant Average Power ProcessingKramer Straube, Christopher Nitta, Raj Amirtharajah, Matthew K. Farrens, Venkatesh Akella. 649-652 [doi]
- Effective Optimization of Branch Predictors through Lightweight SimulationChaobing Zhou, Libo Huang, Tan Zhang, Yongwen Wang, Chengyi Zhang, Qiang Dou. 653-656 [doi]
- CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND FlashMeng Zhang, Fei Wu 0005, Yajuan Du, Chengmo Yang, Changsheng Xie, Jiguang Wan. 657-664 [doi]
- Fast, Ring-Based Design of 3D Stacked DRAMAndrew J. Douglass, Sunil P. Khatri. 665-672 [doi]
- Memory-Bounded Randomness for Hardware-Constrained Encrypted ComputationNektarios Georgios Tsoutsos, Oleg Mazonka, Michail Maniatakos. 673-680 [doi]
- Exploiting Process Variation for Read Performance Improvement on LDPC Based Flash Memory Storage SystemsQiao Li, Liang Shi, Yejia Di, Yajuan Du, Chun Jason Xue, Edwin Hsing-Mean Sha. 681-684 [doi]
- A Design-for-Test Solution for Monolithic 3D Integrated CircuitsAbhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty. 685-688 [doi]