Abstract is missing.
- Session 3 - Clocking techniquesSudhakar Pamarti, Nan Sun. 1 [doi]
- nd-order ΔΣ linearizationHechen Wang, Fa Foster Dai, Hua Wang. 1-4 [doi]
- A 0.951 psrms period jitter, 3.2% modulation range, DSM-free, spread-spectrum PLLHyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon. 1-4 [doi]
- CMOS sensor for dual fluorescence intensity and lifetime sensing using multicycle charge modulationGuoqing Fu, Sameer Sonkusale. 1-4 [doi]
- A 0.8∼1.3 GHz multi-phase injection-locked PLL using capacitive coupled multi-ring oscillator with reference spur suppressionRuixin Wang, Fa Foster Dai. 1-4 [doi]
- Session 27 - Technology directionsChristophe Antoine, Marco Tartagni. 1 [doi]
- An up to 36Gbps analog baseband equalizer and demodulator for mm-wave wireless communication in 28nm CMOSOscar Elisio Mattia, Davide Guermandi, Guy Torfs, Piet Wambacq. 1-4 [doi]
- Analog in-memory subthreshold deep neural network acceleratorLaura Fick, David Blaauw, Dennis Sylvester, Skylar Skrzyniarz, M. Parikh, David Fick. 1-4 [doi]
- Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOSYunzhi Dong, José B. Silva, Qingdong Meng, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Donald Paterson, Jeffrey C. Gealow. 1-4 [doi]
- A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvementXiaowei Han, Qian Jia, Hongbin Sun, Longfei Wang, Huaqiang Wu, YiMao Cai, Feng Zhang, Yongyi Xie, Fangxu Dong, Xiaoguang Wang, Xiaofei Xue, Li Pang, Xiaoqing Zhao, Mengnan Wu, Pu Bai, Qi Liu, Hangbing Lv, Bing Yu, Chao Zhao, He Qian, Ru Huang, Ming Liu, Yumei Zhou, Nanning Zheng, Qiwei Ren. 1-4 [doi]
- A pipelined SAR ADC reusing the comparator as residue amplifierMiguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon, Nan Sun. 1-4 [doi]
- A 2.4mW, 111dB SNR continuous-time ΣΔ ADC with a three-level DEM techniqueKhiem Nguyen, Michael Determan, Sejun Kim. 1-4 [doi]
- Session 19 - High performance and low power frequency generationYanjie Wang, Hua Wang. 1 [doi]
- A 1.2 V, 0.84 pJ/conv.-Step ultra-low power capacitance to digital converter for microphone based auscultationNeelakantan Narasimman, Dipankar Nag, Kevin Chai Tshun Chuan, Tony T. Kim. 1-4 [doi]
- Channel adaptive ADC and TDC for 28 Gb/s PAM-4 digital receiverAurangozeb, A. K. M. Delwar Hossain, Masum Hossain. 1-4 [doi]
- An efficient 4-way-combined 291 GHz signal source with 1.75 mW peak output power in 65 nm CMOSAlit Apriyana, Guangyin Feng, Yang Shang, Jincai Wen, Lingling Sun, Hao Yu. 1-4 [doi]
- Smart-wire: A 0.5V 44uW 0°C to 100°C power-line energy harvesting sensor nodeAdelson Chua, Rico Jossel Maestro, John Cris Jardin, Kristofer Monisit, Renan Nuestro, Ken Bryan Fabay, Bernard Raymond Pelayo, Wes Vernon Lofamia, Joana Rochelle Ortiz, Joy Alinda Madamba, Louis P. Alarcón. 1-4 [doi]
- A precisely-timed energy injection technique achieving 58/10/2μs start-up in 1.84/10/50MHz crystal oscillatorsHani Esmaeelzadeh, Sudhakar Pamarti. 1-4 [doi]
- Energy efficient system architecture for wireless wearable biomedical sensorsYong Lian. 1-33 [doi]
- 2 Terahertz nano-radio in CMOS with 49.3mW peak power consumption supporting 50cm Internet-of-Things communicationTaiyun Chi, Hechen Wang, Min-Yu Huang, Fa Foster Dai, Hua Wang. 1-4 [doi]
- A/D converter fundamentals and trendsHui Pan. 1-102 [doi]
- A 0.7V time-based inductor for fully integrated low bandwidth filter applicationsBraedon Salz, Mrunmay Talegaonkar, Guanghua Shu, Ahmed Elmallah, Romesh Kumar Nandwana, Bibhudatta Sahoo, Pavan Kumar Hanumolu. 1-4 [doi]
- A digital sine-weighted switched-Gm mixer for single-clock power-scalable parallel receiversReda Kasri, Eric A. M. Klumperink, Philippe Cathelin, Eric Toumier, Bram Nauta. 1-4 [doi]
- A 256kb 6T self-tuning SRAM with extended 0.38V-1.2V operating range using multiple read/write assists and VMIN tracking canary sensorsArijit Banerjee, Ningxi Liu, Harsh N. Patel, Benton H. Calhoun, John W. Poulton, C. Thomas Gray. 1-4 [doi]
- An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifierMasaya Miyahara, Akira Matsuzawa. 1-4 [doi]
- Session 6 - RF and millimeter-wave power amplifiers and transmittersAli Shirvani, K. J. Koh. 1 [doi]
- A yield optimization methodology for mixed-signal circuitsAikaterini Papadopoulou, Borivoje Nikolic. 1-4 [doi]
- 12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognitionYoshiaki Deguchi, Toshiki Nakamura, Atsuro Kobayashi, Ken Takeuchi. 1-4 [doi]
- A 980μW 5.2dB-NF current-reused direct-conversion bluetooth-low-energy receiver in 40nm CMOSAmir Hossein Masnadi Shirazi, Hossein Miri Lavasani, Mojtaba Sharifzadeh, Yashar Rajavi, Shahriar Mirabbasi, Mazhareddin Taghivand. 1-4 [doi]
- Analog filter design: Current design techniques and trendsEdgar Sánchez-Sinencio. 1-76 [doi]
- Millimeter-wave full-duplex wireless: Applications, antenna interfaces and systemsTolga Dinc, Harish Krishnaswamy. 1-8 [doi]
- An ultra-low-power wake-up receiver with voltage-multiplying self-mixer and interferer-enhanced sensitivityVivek Mangal, Peter R. Kinget. 1-4 [doi]
- System-on-chip security assurance for IoT devices: Cooperations and conflictsSandip Ray. 1-4 [doi]
- Interference-immune diagnostic quality ECG recording for patient monitoring applicationsArthur Kalb, Yogesh Sharma, Juha Virtanen. 1-4 [doi]
- Achieving higher linearity in precision standard productsNathan Carter. 1-45 [doi]
- Programmable supply boosting techniques for near threshold and wide operating voltage SRAMRajiv V. Joshi, Matthew M. Ziegler. 1-4 [doi]
- An 11.0 bit ENOB, 9.8 fJ/conv.-step noise-shaping SAR ADC calibrated by least squares estimationHarald Garvik, Carsten Wulff, Trond Ytterdal. 1-4 [doi]
- A 92.1% efficient DC-DC converter for ultra-low power microcontrollers with fast wake-upF. Santoro, Rüdiger Kuhn, N. Gibson, N. Rasera, T. Tost, Doris Schmitt-Landsiedel, Ralf Brederlow. 1-4 [doi]
- Session 11 - Wireline building blocksEric Naviasky, Mohammad Hekmat. 1 [doi]
- Hardware for machine learning: Challenges and opportunitiesVivienne Sze, Yu-Hsin Chen, Joel Einer, Amr Suleiman, Zhengdong Zhang. 1-8 [doi]
- SCPA revolution: Linearization of multiphase SCPAsAli Azam, Zhidong Bai, Wen Yuan, Jeffrey S. Walling. 1-8 [doi]
- Session 20 - High-performance low-power wireless receiversJulian Tham, Hossein Miri Lavasani. 1 [doi]
- Jitter injection for on-chip jitter measurement in PI-based CDRsJoshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi. 1-4 [doi]
- A 10-to-650MHz 1.35W class-AB power amplifier with instantaneous supply-switching efficiency enhancementJeffrey Lee, Sudhakar Pamarti, Ramon A. Gomez. 1-4 [doi]
- Autonomy through smart sensors and power electronicsHans Stork. 1 [doi]
- Design with sub-10 nm FinFET technologiesLawrence T. Clark, Vinay Vashishtha. 1-87 [doi]
- A 4-40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOSXuqiang Zheng, Chun Zhang, Fangxu Lv, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang. 1-4 [doi]
- Using quantum emulation for advanced computationBrian R. La Cour, Granville E. Ott, S. Andrew Lanham. 1-8 [doi]
- A -236.3dB FoM sub-sampling low-jitter supply-robust ring-oscillator PLL for clocking applications with feed-forward noise-cancellationShravan S. Nagam, Peter R. Kinget. 1-4 [doi]
- Equalization algorithms in Millimeter wave communication systemsSrevats Laxman. 1-38 [doi]
- A 220-mV input, 8.6 step-up voltage conversion ratio, 10.45-μW output power, fully integrated switched-capacitor converter for energy harvestingLuca Intaschi, Paolo Bruschi, Giuseppe Iannaccone, Francesco Dalena. 1-4 [doi]
- A supposedly clever thing i'll never do againAaron Buchwald. 1-8 [doi]
- Leveraging the strengths of female engineers in today's business environmentSusanne Paul. 1-42 [doi]
- Session 8 - Biomedical circuits and systemsPedram Mohseni, Kaushik Sengupta. 1 [doi]
- Session 24-Milimeter-wave communication circuitsJohn Long, Fa Foster Dai. 1 [doi]
- A power-efficient multi-channel PPG ASIC with 112dB receiver DR for pulse oximetry and NIRSPhilipp Schönle, Schekeb Fateh, Thomas Burger, Qiuting Huang. 1-4 [doi]
- A CMOS 22k-pixel single-cell resolution multi-modality real-time cellular sensing arrayJong Seok Park, Moez Karim Aziz, Sandra Gonzalez, Doohwan Jung, Taiyun Chi, Sensen Li, Hee Cheol Cho, Hua Wang. 1-4 [doi]
- A 0.5V supply, 49nW band-gap reference and crystal oscillator in 40nm CMOSAbhirup Lahiri, Pradeep Badrathwal, Nitin Jain, Kallol Chatterjee. 1-4 [doi]
- Modelling multistability and hysteresis in ESD clamps, memristors and other devicesTianshi Wang. 1-10 [doi]
- A monolithically integrated, optically clocked 10 GS/s sampler with a bandwidth of >30 GHz and a jitter of <30 fs in photonic SiGe BiCMOS technologyB. Krueger, R. E. Makon, O. Landolt, O. Hidri, T. Schweiger, E. Krune, D. Knoll, Stefan Lischke, J. Schulze. 1-4 [doi]
- A 1.2A auto-configurable dual-output switched-capacitor DC-DC regulator with continuous gate-drive modulation achieving <0.01mV/mA cross regulationZhe Hua, Hoi Lee. 1-4 [doi]
- From algorithms to devices: Enabling machine learning through ultra-low-power VLSI mixed-signal array processingSiddharth Joshi, Chul Kim, Sohmyung Ha, Gert Cauwenberghs. 1-9 [doi]
- A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilitiesMuqing Liu, Luke R. Everson, Chris H. Kim. 1-4 [doi]
- 32 Challenge Response Pairs per 1Kbit array for secure chip authenticationQianying Tang, Chen Zhou, Woong Choi, Gyuseong Kang, Jongsun Park, Keshab K. Parhi, Chris H. Kim. 1-4 [doi]
- A 40-Gbps 0.5-pJ/bit VCSEL driver in 28nm CMOS with complex zero equalizerAlireza Sharif Bakhtiar, Michael G. Lee, Anthony Chan Carusone. 1-4 [doi]
- 2, 910fs, 0.5-4GHz injection type SOC PLL with 90dB built-in supply noise rejection in 10nm FinFET CMOSChin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen. 1-4 [doi]
- Low-power CMOS receivers for short reach optical communicationAlireza Sharif Bakhtiar, Michael G. Lee, Anthony Chan Carusone. 1-8 [doi]
- A 255nW ultra-high input impedance analog front-end for non-contact ECG monitoringJinseok Lee, Hyojun Kim, SeongHwan Cho. 1-4 [doi]
- Practical dynamic element matching techniques for 3-level unit elementsKhiem Nguyen. 1-87 [doi]
- Digitally controlled voltage regulator using oscillator-based ADC with fast-transient-response and wide dropout range in 14nm CMOSTarun Mahajan, Ramnarayanan Muthukaruppan, Dheeraj M. Shetty, Sumedha Mangal, Harish K. Krishnamurthy. 1-4 [doi]
- A 350uW 2GHz FBAR transformer coupled Colpitts oscillator with close-in phase noise reductionJabeom Koo, Keping Wang, Richard C. Ruby, Brian P. Otis. 1-4 [doi]
- 2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditionsAdvait Madhavan, Timothy Sherwood, Dmitri B. Strukov. 1-4 [doi]
- A 10-b 2b/cycle 300MS/s SAR ADC with a single differential DAC in 40nm CMOSJeonggoo Song, Xiyuan Tang, Nan Sun. 1-4 [doi]
- Time-based ΑΣADCsPavan Kumar Hanumolu. 1-44 [doi]
- Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologiesSanu Mathew, Sudhir Satpathy, Vikram Suresh, Ram K. Krishnamurthy. 1-4 [doi]
- A background calibrated 28GS/s 8b interleaved SAR ADC in 28nm CMOSM. Q. Le, James Gorecki, Jamal Riani, Jorge Pernillo, A. Tan, K. Gopalakrishnan, Belal Helal, Pulkit Khandelwal, Chang-Feng Loi, Irene Quek, P. Wong, A. Buchwald. 1-4 [doi]
- An isolated DC-DC converter with fully integrated magnetic core transformerTianting Zhao, Yue Zhuo, Baoxing Chen. 1-4 [doi]
- A ±5V, ±10V, ±15V, 4-channel class-G biphasic constant-current stimulatorEdward K. F. Lee. 1-4 [doi]
- ES4-4: Circuit design techniques for fully integrated voltage regulator using switched capacitorsHanh-Phuc Le. 1-69 [doi]
- th-order low-pass filter with +28.8dBm IIP3 using source follower couplingYang Xu, Jason Muhlestein, Un-Ku Moon. 1-4 [doi]
- A dynamically reconfigurable ECG analog front-end with a 2.5 × data-dependent power reductionSomok Mondal, Chung-Lun Hsu, Roozbeh Jafari, Drew A. Hall. 1-4 [doi]
- Multi-phase sub-sampling fractional-N PLL with soft loop switching for fast robust lockingDongyi Liao, Fa Foster Dai, Bram Nauta, Eric A. M. Klumperink. 1-4 [doi]
- RF/analog and mixed-signal design techniques in FD-SOI technologyAndreia Cathelin. 1-53 [doi]
- Design of tunable digital delay cellsYu Chen, Rajit Manohar, Yannis P. Tsividis. 1-4 [doi]
- A start-up boosting circuit with 133× speed gain for 2-transistor voltage referenceDongkwun Kim, Wanyeong Jung, Sechang Oh, Kyojin David Choo, Dennis Sylvester, David Blaauw. 1-4 [doi]
- Energy efficiency maxima for wireless communications: 5G, IoT, and massive MIMOEarl McCune. 1-8 [doi]
- Measurement of high-speed ADCsLukas Kull, Danny Luu. 1-7 [doi]
- A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellationSiladitya Dey 0002, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez. 1-4 [doi]
- Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis ControlChung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai. 1-4 [doi]
- RC-triggered ESD clamp with low turn-on voltageM. Stockinger, R. Mertens. 1-4 [doi]
- Fully tunable software defined DC-DC converter with 3000X output current & 4X output voltage rangesSaurabh Chaubey, Ramesh Harjani. 1-4 [doi]
- A 45-75MHz 197-452µW oscillator with 164.6dB FoM and 2.3psrms period jitter in 65nm CMOSJunheng Zhu, Makrand Mahalley, Guanghua Shu, Woo-seok Choi, Romesh Kumar Nandwana, Ahmed Elkholy, Bibhudatta Sahoo, Pavan Kumar Hanumolu. 1-4 [doi]
- A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BWYi Zhang, Chia-Hung Chen, Tao He, Kazuki Sobue, Koichi Hamashita, Gabor C. Temes. 1-4 [doi]
- An extemal-capacitor-less low-dropout regulator with less than -36dB PSRR at all frequencies from 10kHz to 1GHz using an adaptive supply-ripple cancellation technique to the body-gateYounghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi. 1-4 [doi]
- A front-end ASIC with high-voltage transmit switching and receive digitization for forward-looking intravascular ultrasoundMingliang Tan, Chao Chen, Zhao Chen, Jovana Janjic, Verya Daeichin, Zu-yao Chang, Emile Noothout, Gijs van Soest, Martin D. Verweij, Nico de Jong, Michiel A. P. Pertijs. 1-4 [doi]
- Session 22 - Oversampling data convertersNima Maghari, Ivan O'Connell. 1 [doi]
- Session 15 - Energy-efficient wireless for 5G and IoTWoogeun Rhee, Swaminathan Sankaran. 1 [doi]
- Millimeter-wave power amplifiers & transmittersHossein Hashemi. 1-8 [doi]
- A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn controlKwanseo Park, Woo-Rham Bae, Deog Kyoon Jeong. 1-4 [doi]
- A 74.33 dB SNDR 20 MSPS 2.74 mW pipelined ADC using a dynamic deadzone ring amplifierSpencer Leuenberger, Jason Muhlestein, Hyuk Sun, Praveen Kumar Venkatachala, Un-Ku Moon. 1-4 [doi]
- N-path filters and mixer-first receivers: A reviewEric A. M. Klumperink, Hugo J. Westerveld, Bram Nauta. 1-8 [doi]
- A 3-7GHz 4-element digital modulated polar phased-array transmitter with 0.35° phase resolution and 38.2% peak system efficiencyHuizhen Jenny Qian, Jian Orion Liang, Nianyong Zhu, Peng Gao, Xun Luo. 1-4 [doi]
- Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltageSamantak Gangopadhyay, Saad Bin Nasir, Hoan Nguyen, Jihoon Jeong, Francois Atallah, Keith A. Bowman, Arijit Raychowdhury. 1-4 [doi]
- Session 5 - Memory for emerging applicationsMuhammad Khellah, Rajiv Joshi. 1 [doi]
- On-chip transformer design and application to RF and mm-wave front-endsJohn R. Long. 1-43 [doi]
- Session 17 non-traditional computingAxel Thomsen, Paul Billig. 1 [doi]
- Session 12-Analog techniques INagendra Krishnapura, Ken Suyama. 1 [doi]
- Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLsEythan Familier, Ian Galton. 1-4 [doi]
- A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOSQiwei Wang, Hajime Shibata, Anthony Chan Carusone, Antonio Liscidini. 1-4 [doi]
- An area-efficient microcontroller with an instruction-cache transformable to an ambient temperature sensor and a physically unclonable functionTeng Yang, Jiangyi Li, Minhao Yang, Peter R. Kinget, Mingoo Seok. 1-4 [doi]
- Integrated DC-DC converter designRamesh Harjani. 1-92 [doi]
- mmWave LO distribution insightsAmr Fahim. 1-72 [doi]
- Flexible selfbiased 66.7nJ/c.s. 6bit 26S/s successive-approximation C-2C ADC with offset cancellation using unipolar Metal-Oxide TFTsNikolaos Papadopoulos, Florian De Roose, Yi-Cheng Lai, Jan-Laurens P. J. van der Steen, Marc Ameys, Wim Dehaene, Jan Genoe, Kris Myny. 1-4 [doi]
- Session 2 - Wireline techniques for advanced modulation schemesSudip Shekhar, Tod Dickson. 1 [doi]
- Temperature-insensitive analog vector-by-matrix multiplier based on 55 nm NOR flash memory cellsXinjie Guo, Farnood Merrikh-Bayat, Mirko Prezioso, Y. Chen, B. Nguyen, N. Do, Dmitri B. Strukov. 1-4 [doi]
- Session 4 - Modeling and measurement of mixed-signal circuitsColin McAndrew, Tetsuya Iizuka. 1 [doi]
- A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modesSeong Joong Kim, Woo-seok Choi, Robert C. N. Pilawa-Podgurski, Pavan Kumar Hanumolu. 1-4 [doi]
- An offset-cancelling four-phase voltage sense amplifier for resistive memories in 14nm CMOSAvishek Biswas, Umut Arslan, Fatih Hamzaoglu, Anantha P. Chandrakasan. 1-4 [doi]
- Session 13 - Security circuits and systemsSwaroop Ghosh, Xin Li 0001. 1 [doi]
- A 10 GHz 56 fsrms-integrated-jitter and -247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOSXuqiang Zheng, Fangxu Lv, Feng Zhao, Shigang Yue, Chun Zhang, Ziqiang Wang, Fule Li, Hanjun Jiang, Zhihua Wang. 1-4 [doi]
- A 6-bit 0.81mW 700-MS/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibrationYeonam Yoon, Nan Sun. 1-4 [doi]
- A scalable architecture for fully integrated multi-TV tunersM. H. Koroglu, A. L. Coban, V. M. Pereira, F. Barale, S. X. Wu, W. Yu, R. Sun, K. Pentakota. 1-4 [doi]
- Session 21 - Analog techniques IIFarhan Adil, Jiangfeng Wu. 1 [doi]
- Design of miniaturized wireless power receivers for mm-sized implantsChul Kim, Sohmyung Ha, Abraham Akinin, Jiwoong Park, Rajkumar Kubendran, Hui Wang, Patrick P. Mercier, Gert Cauwenberghs. 1-8 [doi]
- 2 SAR ADC in 65nm using novel residue boostingJoonsung Park, Krishnaswamy Nagaraj, Mikel Ash, Ajay Kumar. 1-4 [doi]
- A 73dB SNDR 20MS/s 1.28mW SAR-TDC using hybrid two-step quantizationJason Muhlestein, Spencer Leuenberger, Hyuk Sun, Yang Xu, Un-Ku Moon. 1-4 [doi]
- A 6.1mW 5Mb/s 2.4GHz transceiver with F-OOK modulation for high bandwidth and energy efficienciesYining Zhang, Ranran Zhou, Woogeun Rhee, Zhihua Wang. 1-4 [doi]
- Session 7 - Data converter techniquesAyman Shabra, Dong-Young Chang. 1 [doi]
- A digital pulse width modulation closed loop control LDMOS gate driver for LED drivers implemented in a 0.18 μm HV CMOS technologySebastian Strache, Leo Rolff, Stefan Dietrich, Michael Hanhart, Tobias Zekorn, Ralf Wunderlich, Stefan Heinen. 1-4 [doi]
- A CMOS pixel design with binary space-time exposure encoding for computational imagingYi Luo, Shahriar Mirabbasi. 1-4 [doi]