Table of Contents

• Power-Aware Test Data Compression for Embedded IP CoresNabil Badereddine, Zhanglei Wang, Patrick Girard 0001, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault. 5-10 [doi]
• A Scan Chain Adjustment Technology for Test Power ReductionJia Li, Yu Hu 0001, Xiaowei Li 0001. 11-16 [doi]
• TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test StructureYoubean Kim, DongSup Song, Kicheol Kim, Incheol Kim, Sungho Kang. 17-24 [doi]
• An Enhanced SRAM BISR Design with Reduced Timing PenaltyLi-Ming Denq, Tzu-chiang Wang, Cheng-Wen Wu. 25-30 [doi]
• Memory Fault Simulator for Static-Linked FaultsAlfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 31-36 [doi]
• Test/Repair Area Overhead Reduction for Small Embedded SRAMsBaosheng Wang, Qiang Xu. 37-44 [doi]
• Statistical Linearity Calibration of Time-To-Digital Converters Using a Free-Running Ring OscillatorJochen Rivoir. 45-50 [doi]
• Histogram Based Testing Strategy for ADCHsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang. 51-54 [doi]
• Detection of Interconnect Open Faults with Unknown Values by Ramp Voltage ApplicationYukiya Miura. 55-62 [doi]
• Delta-IDDQ Testing of Resistive Short DefectsPiet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker 0001. 63-68 [doi]
• A BIC Sensor Capable of Adjusting IDDQ Limit in TestsMasato Nakanishi, Masaki Hashizume, Hiroyuki Yotsuyanagi, Yukiya Miura. 69-74 [doi]
• ATPG for Dynamic Burn-In Test in Full-Scan CircuitsAlfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto. 75-82 [doi]
• Spectral RTL Test Generation for Gate-Level Stuck-at FaultsNitin Yogi, Vishwani D. Agrawal. 83-88 [doi]
• An Observability Branch Coverage Metric Based on Dynamic Factored Use-Define ChainsTao Lv 0001, Ling-Yi Liu, Yang Zhao, Hua-wei Li, Xiao-Wei Li. 89-94 [doi]
• A Functional Fault Model with Implicit Fault Effect Propagation RequirementsIrith Pomeranz, Srinivas Patil, Praveen Parvathala. 95-102 [doi]
• The Potential and Limitation of Probability-Based Combinational Equivalence CheckingShih-Chieh Wu, Chun-Yao Wang, Jan-an Hsieh. 103-108 [doi]
• Verification Methodology for Self-Repairable Memory SystemsJin-Fu Li, Chun-Hsien Wu. 109-114 [doi]
• A Soft Error Tolerant LUT Cascade EmulatorHiroki Nakahara, Tsutomu Sasao. 115-124 [doi]
• To Overtest Or Not To Overtest - More Questions Than AnswersIrith Pomeranz. 125 [doi]
• How to Perform DFT Timing in Mixed Signal Designs, from 28 Hours to 7 MinutesPaul Wong, Jing Jiang. 126 [doi]
• An Application of IDD Spectrum Testing Method to the Fault AnalysisKazuhiro Sakaguchi. 127 [doi]
• iDEN Phone System Test: An Automation ApproachMuhammad Aiman Mazlan, Ong Kein Wei, Cindy Phang Sim Sim. 128 [doi]
• Development of practical ATPG tool with flexible interfaceMasayoshi Yoshimura, Yusuke Matsunaga. 129 [doi]
• Mentor Graphics DFT to Navigate Nanometer Test ChallengesGreg Aldrich, Ron Press, Takeo Kobayashi, Tatsuo Sakajiri. 130 [doi]
• The Application of BIST-Aided Scan Test for Real ChipsHideaki Konishi, Michiaki Emori, Takahisa Hiraide. 131 [doi]
• A Scalable Architecture for On-Chip Compression: Options and Trade-OffsAnis Uzzaman, Brion L. Keller, Vivek Chickermane. 132 [doi]
• Practical Needs and Wants for Silicon Debug and DiagnosisFidel Muradali. 135 [doi]
• Timing-Aware ATPG for High Quality At-speed Testing of Small Delay DefectsXijiang Lin, Kun-Han Tsai, Chen Wang 0014, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo. 139-146 [doi]
• Not all Delay Tests Are the Same - SDQL Model Shows True-TimeAnis Uzzaman, Mick Tegethoff, Bibo Li, Kevin Mc Cauley, Shuji Hamada, Yasuo Sato. 147-152 [doi]
• At-Speed Testing with Timing Exceptions and Constraints-Case StudiesDhiraj Goswami, Kun-Han Tsai, Mark Kassab, Takeo Kobayashi, Janusz Rajski, Bruce Swanson, Darryl Walters, Yasuo Sato, Toshiharu Asaka, Takashi Aikyo. 153-162 [doi]
• A New Scan Design Technique Based on Pre-Synthesis Thru FunctionsChia Yee Ooi, Hideo Fujiwara. 163-168 [doi]
• Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test CoverageSying-Jyan Wang, Kuo-Lin Peng, Katherine Shu-Min Li. 169-174 [doi]
• On the Replacement of Scan Chain Inputs by Primary Input VectorsIrith Pomeranz, Sudhakar M. Reddy. 175-182 [doi]
• Study of N-Detectability in QCA DesignsBiplab K. Sikdar. 183-188 [doi]
• A Design of Pipelined Carry-dependent Sum Adder With its Self-checking StructureMing Li, Shiyi Xu, Jialin Cao, Feng Ran, Shiwei Ma. 189-194 [doi]
• ESTA: An Efficient Method for Reliability Enhancement of RT-Level DesignsNaghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi. 195-202 [doi]
• Interconnect Open Defect Diagnosis with Physical InformationWei Zou, Wu-Tung Cheng, Sudhakar M. Reddy. 203-209 [doi]
• Defect Diagnosis - Reasoning MethodologyYasuo Sato, Kazushi Sugiura, Reisuke Shimoda, Yutaka Yoshizawa, Kenji Norimatsu, Masaru Sanada. 209-214 [doi]
• Diagnosis of delay faults due to resistive bridges, delay variations and defectsLei Wang, Sandeep K. Gupta, Melvin A. Breuer. 215-224 [doi]
• Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time ReductionPo-Chang Tsai, Sying-Jyan Wang. 225-230 [doi]
• Test data compression based on clustered random access scanYu Hu 0001, Cheng Li, Jia Li, Yinhe Han, Xiao-Wei Li, Wei Wang, Hua-wei Li, Laung-Terng Wang, Xiaoqing Wen. 231-236 [doi]
• Efficiently Utilizing ATE Vector Repeat for Compression by Scan Vector DecompositionJinkyu Lee 0005, Nur A. Touba. 237-244 [doi]
• A Statistical Digital Equalizer for Loopback-based Linearity Test of Data ConvertersHongjoong Shin, Jiseon Park, Jacob A. Abraham. 245-250 [doi]
• A Digital BIST Methodology for Spread Spectrum Clock GeneratorsMaohsuan Chou, Jen-Chien Hsu, Chauchin Su. 251-254 [doi]
• A Cost Effective Output Response Analyzer for \sum - \delta Modulation Based BIST SystemsHao-Chiao Hong, Sheng-Chuan Liang. 255-264 [doi]
• Test Generation for Weak Resistive BridgesShahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer. 265-272 [doi]
• A Specific ATPG technique for Resistive Open with Sequence Recursive DependencyMichel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker 0001. 273-278 [doi]
• An Effective Test Pattern Generation for Testing Signal IntegrityYongJoon Kim, Myung-Hoon Yang, Youngkyu Park, Daeyeal Lee, Sungho Kang. 279-286 [doi]
• A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested LoopsXiaogang Du, Nilanjan Mukherjee 0001, Chris Hill, Wu-Tung Cheng, Sudhakar M. Reddy. 287-292 [doi]
• An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table TestingArmin Alaghi, Mahnaz Sadoughi Yarandi, Zainalabedin Navabi. 293-298 [doi]
• Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan ArhcitectureHideo Fujiwara, Jiaguang Sun, Krishnendu Chakrabarty, Yang Zhao 0001, Dong Xiang. 299-306 [doi]
• Enhanced A/D Converter Signal-to-Noise-Ratio Testing in the Presence of Sampling Clock JitterShalabh Goyal, Abhijit Chatterjee, Yanan Shieh. 307-312 [doi]
• A Self-Referred Clock Jitter Measurement Circuit in Wide Frequency RangeChung-Yi Li, Chia-yuan Chou, Tsin-Yuan Chang. 313-317 [doi]
• A Random Jitter Extraction Technique in the Presence of Sinusoidal JitterJiun-Lang Huang. 318-326 [doi]
• Low Power Oriented Test Modification and Compression Techniques for Scan Based Core TestingTerumine Hayashi, Naotsugu Ikeda, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita. 327-332 [doi]
• An Efficient Test Pattern Selection Method for Improving Defect Coverage with Reduced Test Data Volume and Test Application TimeZhanglei Wang, Krishnendu Chakrabarty. 333-338 [doi]
• Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICsRajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell. 339-348 [doi]
• Fanout-based fault diagnosis for open faults on pass/fail informationKoji Yamazaki, Yuzo Takamatsu. 349-353 [doi]
• Diagnosis of Transistor Shorts in Logic Test EnvironmentYoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu. 354-359 [doi]
• The Next Step in Volume Scan Diagnosis: Standard Fail Data FormatAndreas Leininger, Ajay Khoche, Martin Fischer 0002, Nagesh Tamarapalli, Wu-Tung Cheng, Randy Klingenberg, Wu Yang. 360-368 [doi]
• DFT of the Cell Processor and its Impact on EDA Test SoftwarLouis Bushard, Nathan Chelstrom, Steven Ross Ferguson, Brion Keller. 369-374 [doi]
• Design for Testability of Software-Based Self-Test for ProcessorsMasato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara. 375-380 [doi]
• Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC MethodologyBrian Foutz, Vivek Chickermane, Bing Li, Harry Linzer, Gary Kunselman. 381-388 [doi]
• Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical CodingKazuteru Namba, Hideo Ito. 389-394 [doi]
• BCH-based Compactors of Test Responses with Controllable MasksTaweesak Reungpeerakul, Xiaoshu Qian, Samiha Mourad. 395-401 [doi]
• Expansion of Convolutional Compactors over Galois FieldMasayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki. 401-408 [doi]
• Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory TesterYoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara. 409-414 [doi]
• Early Life Cycle Yield Learning for Nanometer Devices Using Volume Yield Diagnostics AnalysisSanae Seike, Ken Namura, Yukio Ohya, Anis Uzzaman, Shinichi Arima, Dale Meehl, Vivek Chickermane, Azumi Kobayashi, Satoshi Tanaka, Hiroyuki Adachi. 415-420 [doi]
• Reducing Scan Test Data Volume and Time: A Diagnosis Friendly Finite Memory CompactorSverre Wichlund, Einar J. Aas. 421-430 [doi]
• Testing Hierarchical Network-on-Chip Systems with Hard Cores Using Bandwidth Matching and On-Chip Variable ClockingChunsheng Liu. 431-436 [doi]
• An External Test Approach for Network-on-a-Chip SwitchesJaan Raik, Vineeth Govind, Raimund Ubar. 437-442 [doi]
• Plug once, test everythingAriel Sabiguero Yawelak, César Viho. 443-448 [doi]