Po-Chang Tsai - researchr alias

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Viewing Publication 1 - 5 from 5

2008

Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reductionPo-Chang Tsai, Sying-Jyan Wang. iet-cdt, 2(6):434-444, 2008. [doi]

2007

Test Data Compression for Minimum Test Application TimePo-Chang Tsai, Sying-Jyan Wang, Ching-Hung Lin, Tung-Hua Yeh. jise, 23(6):1901-1909, 2007. [doi]

Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan ArchitectureSying-Jyan Wang, Po-Chang Tsai, Hung-Ming Weng, Katherine Shu-Min Li. ats 2007: 95-100 [doi]

2006

Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time ReductionPo-Chang Tsai, Sying-Jyan Wang. ats 2006: 225-230 [doi]

2005

FSM-based programmable memory BIST with macro commandPo-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang. mtdt 2005: 72-77 [doi]

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