Abstract is missing.
- Advanced simulation technology and its application in memory design and verificationBruce McGaughy, S. Wünsche, K. K. Hung. [doi]
- Zero capacitor embedded memory technology for system on chipSerguei Okhonin, Pierre Fazan, Mark-Eric Jones. [doi]
- Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memoryKung-Hong Lee, Shih-Chen Wang, Ya-Chin King. 3-8 [doi]
- A novel CMOS compatible embedded nonvolatile memory with zero process adderMatthew J. Breitwisch, Chung Hon Lam, Jeffrey B. Johnson, Steven W. Mittl, Jian W. Zhu. 9-12 [doi]
- Embedded OTP fuse in CMOS logic processChing-Yuan Lin, Chung-Hung Lin, Chien-Hung Ho, Wei-Wu Liao, Shu-Yueh Lee, Ming-Chou Ho, Shih-Chen Wang, Shih-Chan Huang, Yuan-Tai Lin, Charles Ching-Hsiang Hsu. 13-15 [doi]
- Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding techniqueMeng-Fan Chang, Kuei-Ann Wen, Ding-Ming Kwai. 16-21 [doi]
- A nor-type MLC ROM with novel sensing scheme for embedded applicationsStar Sung, Thomas Chang, Juei Lung Chen. 22-25 [doi]
- Dielectric tunnel parameters of CoFe/Al-O/CoFe in MTJ for 1T1MTJ MRAM applicationsSimon C. Li, J. P. Su, T. H. Wu, J. M. Lee, M. F. Shu. 29-34 [doi]
- A novel single poly-silicon EEPROM using trench floating gateMeng-Yi Wu, Shin-Chang Feng, Ya-Chin King. 35-37 [doi]
- An investigation into three-level ferroelectric memoryKamlesh R. Raiter, Bruce F. Cockburn. 38-43 [doi]
- A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capabilityValerie Lines, Robert McKenzie, Hakjune Oh, Hong-Beom Pyeon, Matthew Dunn, Susan Palapar, Susan Coleman, Peter Nyasulu, Tony Mai, Seanna Pike, John McCready, Jody Defazio, Jin Ki Kim, Robert Penchuk, Zvika Greenfield, Fredy Lange, Alberto Mandler, Eric C. Jones, Matthew Silverstein. 47-51 [doi]
- A high speed BIST architecture for DDR-SDRAM testingSheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee. 52-57 [doi]
- A programmable built-in self-test for embedded DRAMsShibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya. 58-63 [doi]
- Full-speed field programmable memory BIST supporting multi-level loopingXiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy. 67-71 [doi]
- FSM-based programmable memory BIST with macro commandPo-Chang Tsai, Sying-Jyan Wang, Feng-Ming Chang. 72-77 [doi]
- DFT architecture for a dynamic fault model of the embedded mask ROM of SOCYang-Han Lee, Yih-Guang Jan, Jei-Jung Shen, Shian-Wei Tzeng, Ming-Hsueh Chuang, Jheng-Yao Lin. 78-82 [doi]
- A complete memory address generator for scan based March algorithmsWei-Lun Wang, Kuen-Jong Lee. 83-88 [doi]
- Software based in-system memory test for highly available systemsAmandeep Singh, Debashish Bose, Sandeep Darisala. 89-94 [doi]
- A systematic approach to reducing semiconductor memory test time in mass productionJen-Chieh Yeh, Shyr-Fen Kuo, Cheng-Wen Wu, Chih-Tsun Huang, Chao-Hsun Chen. 97-102 [doi]
- Impact of stresses on the fault coverage of memory testsSaid Hamdioui, Zaid Al-Ars, Ad J. Van de Goor, Rob Wadsworth. 103-108 [doi]
- DFT techniques for memory macro with built-in ECCKeiichi Kushida, Nobuaki Otsuka, Osamu Hirabayashi, Yasuhisa Takeyama. 109-114 [doi]
- An error detection and correction scheme for RAMs with partial-write functionJin-Fu Li, Yu-Jane Huang. 115-120 [doi]
- A BIRA algorithm for embedded memories with 2D redundancyShyue-Kung Lu, Yu-Cheng Tsai, Shih-Chang Huang. 121-126 [doi]
- Distributed data-retention power gating techniques for column and row co-controlled embedded SRAMChung-Hsien Hua, Tung-Shuan Cheng, Wei Hwang. 129-134 [doi]
- A low-power SRAM design using quiet-bitline architectureShin-Pao Cheng, Shi-Yu Huang. 135-139 [doi]
- Measurement and characterization of 6T SRAM cell currentChing-Hua Hsiao, Ding-Ming Kwai. 140-145 [doi]
- Reliability enhancement of CMOS SRAMsChin-Long Wey, Meng-Yao Liu, Shaolei Quan. 146-151 [doi]