Sheng-Chih Shen, Hung-Ming Hsu, Yi-Wei Chang, Kuen-Jong Lee. A high speed BIST architecture for DDR-SDRAM testing. In 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan. pages 52-57, IEEE Computer Society, 2005. [doi]
Abstract is missing.