A low-power SRAM design using quiet-bitline architecture

Shin-Pao Cheng, Shi-Yu Huang. A low-power SRAM design using quiet-bitline architecture. In 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan. pages 135-139, IEEE Computer Society, 2005. [doi]

Abstract

Abstract is missing.