Shin-Pao Cheng, Shi-Yu Huang. A low-power SRAM design using quiet-bitline architecture. In 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan. pages 135-139, IEEE Computer Society, 2005. [doi]
@inproceedings{ChengH05-1,
title = {A low-power SRAM design using quiet-bitline architecture},
author = {Shin-Pao Cheng and Shi-Yu Huang},
year = {2005},
doi = {10.1109/MTDT.2005.10},
url = {http://doi.ieeecomputersociety.org/10.1109/MTDT.2005.10},
researchr = {https://researchr.org/publication/ChengH05-1},
cites = {0},
citedby = {0},
pages = {135-139},
booktitle = {13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan},
publisher = {IEEE Computer Society},
isbn = {0-7695-2313-7},
}