A low-power SRAM design using quiet-bitline architecture - researchr publication authors

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Shin-Pao Cheng, Shi-Yu Huang. A low-power SRAM design using quiet-bitline architecture. In 13th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2005), 3-5 August 2005, Taipei, Taiwan. pages 135-139, IEEE Computer Society, 2005. [doi]

This author has not been identified. Look up 'Shin-Pao Cheng' in GoogleThis author has not been identified. Look up 'Shi-Yu Huang' in Google

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