Abstract is missing.
- Hot Chips 2012 AMD "Trinity" APUSebastien Nussbaum. 1-40 [doi]
- Efficient, precise-restartable program execution on future multicoresGagan Gupta, Srinath Sridharan, Gurindar S. Sohi. 1-3 [doi]
- Intel® Xeon Phi coprocessor (codename Knights Corner)George Chrysos. 1-31 [doi]
- SPARC64™ X: Fujitsu's new generation 16 core processor for the next generation UNIX serversTakumi Maruyama. 1-20 [doi]
- The Intel® Xeon® processor E5 family architecture, power efficiency, and performanceJeff Gilbert, Mark Rowland. 1-25 [doi]
- An IA-32 processor with a wide voltage operating range in 32nm CMOSGregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar. 1-37 [doi]
- Power management of the third generation intel core micro architecture formerly codenamed ivy bridgeSanjeev Jahagirdar, George Varghese, Inder Sodhi, Ryan Wells. 1-49 [doi]
- Visconti2 - a heterogeneous multi-core SoC for image-recognition applicationsMasato Uchiyama, Hideho Arakida, Yasuki Tanabe, Tsukasa Ike, Takanori Tamai, Moriyasu Banno. 1-22 [doi]
- Low power and high performance 3-D multimedia platformPo-Han Huang, Chi-Hung Lin, Hsien-Ching Hsieh, Huang-Lun Lin, Shing-Wu Tung. 1-3 [doi]
- Welcome to Hot Chips 24Rumi Zahir, Christos Kozyrakis. 1-11 [doi]
- Hot Chips: Stacking tutorialChoon Lee. 1 [doi]
- ProAptiv: Efficient performance on a fully-synthesizable coreRanganathan Sudhakar. 1-27 [doi]
- "Jaguar" AMD's next generation low power x86 coreJeff Rupley. 1-20 [doi]
- Cloud transforms it Big Data transforms businessPat Gelsinger. 1-30 [doi]
- Floating point processing using FPGAsMichael Parker. 1-31 [doi]
- Reducing transistor variability for high performance low power chipsRobert Rogenmoser. 1-19 [doi]
- Optical backplanes with 3D integrated photonics?Ephrem Wu. 1-20 [doi]
- SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-socketsSebastian Turullols, Ram Sivaramakrishnan. 1-37 [doi]
- The model is not enough: Understanding energy consumption in mobile devicesJames Bornholt, Todd Mytkowicz, Kathryn S. McKinley. 1-3 [doi]
- High performance State Retention with Power Gating applied to CPU subsystems - design approaches and silicon evaluationDavid Flynn. 1-3 [doi]
- Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systemsRonald G. Dreslinski, Korey Sewell, Thomas Manville, Sudhir Satpathy, Nathaniel Ross Pinckney, Geoffrey Blake, Michael Cieslak, Reetuparna Das, Thomas F. Wenisch, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge. 1-44 [doi]
- Xilinx SSI technology concept to silicon development overviewShankar Lakka. 1-22 [doi]
- SOC programming tutorialNeil Trevett. 1-71 [doi]
- The surround computing ERAMark Papermaster. 1-26 [doi]
- Roadmap for design and EDA infrastructure for 3D productsRiko Radojcic. 1-21 [doi]
- AMD Radeon™ HD 7970 with graphics core next (GCN) architectureMike Mantor. 1-35 [doi]
- Prototyping the DySER specialization architecture with OpenSPARCJesse Benson, Ryan Cofell, Chris Frericks, Venkatraman Govindaraju, Chen-Han Ho, Zachary Marzec, Tony Nowatzki, Karu Sankaralingam. 1-3 [doi]
- IBM zNext - the 3rd generation high frequency microprocessor chipChung-Lung Shum. 1-18 [doi]
- ADI's revolutionary BF60x vision focused digital signal processor system on chip: 25 billion operations/sec @ 80 mW and zero bandwidthRobert Bushey. 1-24 [doi]
- High performance and efficient single-chip small cell base station SoCKin-Yip Liu. 1-29 [doi]
- FSM™ femtocell station modemLuca Blessent. 1-17 [doi]
- Centip3De: A 64-core, 3D stacked, near-threshold systemRonald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw. 1-30 [doi]
- X-Gene™: 64-bit ARM CPU and SoCParamesh Gopi, Gaurav Singh, Greg Favor. 1-19 [doi]
- FPGAs with 28Gb/s transceivers built with heterogeneous stacked-silicon interconnectsEphrem Wu, Suresh Ramalingam. 1-20 [doi]
- FPGA augmented ASICs: The time has comeDavid Riddoch, Steve Pope. 1-44 [doi]
- Medfield smartphone SOC Intel® Atom Z2460 processorRumi Zahir. 1-20 [doi]
- The future of wireless networkingMarcus Weldon. 1-24 [doi]
- ArcSoft multi-frame technologiesSean Mao. 72-81 [doi]
- Touch-free technologyItay Katz. 82-92 [doi]
- Augmented realityBen Blachnitzky. 93-103 [doi]
- Sensor fusion mobile platform challenges and future directionsJim Steele. 104-114 [doi]