Abstract is missing.
- Recent technological trends and their impact on system designPratap Pattnaik. 1-2 [doi]
- An analysis of the effects of miss clustering on the cost of a cache missThomas R. Puzak, Allan Hartstein, Philip G. Emma, Viji Srinivasan, Jim Mitchell. 3-12 [doi]
- Analysis of hardware prefetching across virtual page boundariesRonald G. Dreslinski, Ali G. Saidi, Trevor N. Mudge, Steven K. Reinhardt. 13-22 [doi]
- Unified microprocessor core storageAlbert Meixner, Daniel J. Sorin. 23-34 [doi]
- Accelerating memory decryption and authentication with frequent value predictionWeidong Shi, Hsien-Hsin S. Lee. 35-46 [doi]
- Evaluating the potential of multithreaded platforms for irregular scientific computationsJarek Nieplocha, Andrès Márquez, John Feo, Daniel G. Chavarría-Miranda, George Chin Jr., Chad Scherrer, Nathaniel Beagley. 47-58 [doi]
- Parallel genomic sequence-search on a massively parallel systemOystein Thorsen, Brian E. Smith, Carlos P. Sosa, Karl Jiang, Heshan Lin, Amanda E. Peters, Wu-chun Feng. 59-68 [doi]
- Scaling time warp-based discrete event execution to 104 processors on a ::::Blue Gene:::: supercomputerKalyan S. Perumalla. 69-76 [doi]
- General floorplan for reversible quantum-dot cellular automataSarah E. Murphy, Erik DeBenedictis, Peter M. Kogge. 77-82 [doi]
- Automated generation of layout and control for quantum circuitsMark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz. 83-94 [doi]
- Models for parallel and hierarchical computationGianfranco Bilardi. 95-96 [doi]
- By-passing the out-of-order execution pipeline to increase energy-efficiencyHans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat. 97-104 [doi]
- Computational and storage power optimizations for the O-GEHL branch predictorKaveh Aasaraai, Amirali Baniasadi, Ehsan Atoofian. 105-112 [doi]
- Adaptive VP decay: making value predictors leakage-efficient designs for high performance processorsJuan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras. 113-122 [doi]
- An intra-task dvfs technique based on statistical analysis of hardware eventsHiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura. 123-130 [doi]
- Fast compiler optimisation evaluation using code-feature based performance predictionChristophe Dubach, John Cavazos, Björn Franke, Grigori Fursin, Michael F. P. O Boyle, Olivier Temam. 131-142 [doi]
- Identifying potential parallelism via loop-centric profilingTipp Moseley, Daniel A. Connors, Dirk Grunwald, Ramesh Peri. 143-152 [doi]
- System management software for virtual environmentsGeoffroy Vallée, Thomas Naughton, Stephen L. Scott. 153-160 [doi]
- A unified evaluation framework for coarse grained reconfigurable array architecturesGrigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis. 161-172 [doi]
- Assessing the potential of hybrid hpc systems for scientific applications: a case studyDaniel G. Chavarría-Miranda, Andrès Márquez. 173-182 [doi]
- Reconfigurable hybrid interconnection for static and dynamic scientific applicationsShoaib Kamil, Ali Pinar, Daniel Gunter, Michael Lijewski, Leonid Oliker, John Shalf. 183-194 [doi]
- The quantum challenge to computer sciencePhilippe Jorrand. 195-196 [doi]
- Design and implementation of a stream-based distributedcomputing platform using graphics processing unitsShinichi Yamagiwa, Leonel Sousa. 197-204 [doi]
- Data buffering optimization methods toward a uniform programming interface for gpu-based applicationsShinichi Yamagiwa, Leonel Sousa, Diogo Antão. 205-212 [doi]
- Fuce: the continuation-based multithreading processorSatoshi Amamiya, Masaaki Izumi, Takanori Matsuzaki, Ryuzo Hasegawa, Makoto Amamiya. 213-224 [doi]
- Scalability of continuation-based fine-grained multithreading in handling multiple I/O requests on FUCEShigeru Kusakabe, Mitsuhiro Aono, Masaaki Izumi, Satoshi Amamiya, Yoshinari Nomura, Hideo Taniguchi, Makoto Amamiya. 225-236 [doi]
- Memory-miser: a performance-constrained runtime system for power-scalable clustersMatthew E. Tolentino, Joseph Turner, Kirk W. Cameron. 237-246 [doi]
- Performance/area efficiency in chip multiprocessors with micro-cachesMichela Becchi, Mark A. Franklin, Patrick Crowley. 247-258 [doi]
- Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocolsEhsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai. 259-266 [doi]
- Converting massive TLP to DLP: a special-purpose processor for molecular orbital computationsTirath Ramdas, Gregory K. Egan, David Abramson, Kim Baldridge. 267-276 [doi]
- Massively parallel processing on a chipPhilippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser. 277-286 [doi]