Abstract is missing.
- Determination of on-chip temperature gradients on reconfigurable hardwareCarsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner, Jürgen Becker. 1-8 [doi]
- Hardware implementation of the GPS authenticationMickaël Dardaillon, Cédric Lauradoux, Tanguy Risset. 1-6 [doi]
- A memory efficient IPv6 lookup engine on FPGADa Tong, Yi-Hua E. Yang, Viktor K. Prasanna. 1-6 [doi]
- Power-efficient and scalable virtual router architecture on FPGASwapnil Haria, Thilan Ganegedara, Viktor K. Prasanna. 1-7 [doi]
- A design assembly framework for FPGA back-end accelerationTannous Frangieh, Peter Athanas. 1-6 [doi]
- Optimizing inter-FPGA communication by automatic channel adaptationJohannes Romoth, Dirk Jungewelter, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert. 1-7 [doi]
- Versatile FPGA-based locomotion platform for legged robotsJose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Horacio Rostro-González. 1-6 [doi]
- A novel physical defects recovery technique for FPGA-IP coresYuki Nishitani, Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 1-7 [doi]
- An efficient and scalable architecture for real-time distortion removal and rectification of live camera imagesMatthias Pohl, Michael Schaeferling, Gundolf Kiefer, Plamen Petrow, Egmont Woitzel, Frank Papenfus. 1-7 [doi]
- Adapting communication for adaptable processors: A multi-axis reconfiguration approachPaulo C. Santos, Gabriel L. Nazar, Luigi Carro, Fakhar Anjam, Stephan Wong. 1-6 [doi]
- An automated test framework for experimenting with stochastic behavior in reconfigurable logicAlex Aa. Birklykke, Yannick Le Moullec, Lars K. Alminde, Ramjee Prasad. 1-6 [doi]
- An implementation of a directory protocol for a cache coherent system on FPGAsVincent Mirian, Paul Chow. 1-6 [doi]
- Comparison of processing performance and architectural efficiency metrics for FPGAs and GPUs in 3D Ultrasound Computer TomographyMatthias Birk, Matthias Balzer, Nicole V. Ruiter, Jürgen Becker. 1-7 [doi]
- A multi-core FPGA-based SoC architecture with domain segregationDaniel Kliem, Sven-Ole Voigt. 1-7 [doi]
- Keynote 1 - The once and future FPGA: The confluence of configurable processing and reconfigurable technologyGrant Martin. 1 [doi]
- Design and analysis of layered coarse-grained reconfigurable architectureZoltán Endre Rákossy, Tejas Naphade, Anupam Chattopadhyay. 1-6 [doi]
- Synchronized-transfer-level design methodology applied to hardware matrix multiplicationMarc-André Daigneault, Jean-Pierre David. 1-7 [doi]
- Keynote 2 - "Reconfigurable Computing and Trust: Foundational technologies to enable trusted reconfigurable platforms"Eric Sivertson. 1 [doi]
- Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case studyGilberto Ochoa-Ruiz, O. Labbani-Narsis, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser. 1-8 [doi]
- A VLSI architecture for the K-best Sphere-Decoder in MIMO systemsPedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García. 1-6 [doi]
- Multi-FPGA prototyping environment: Large benchmark generation and signals routingMariem Turki, Habib Mehrez, Zied Marrakchi. 1-6 [doi]
- A model design of a 2560-channel neural spike detection platformNashwa Elaraby, Iyad Obeid. 1-6 [doi]
- A case study of streaming storage format for sparse matricesShweta Jain-Mendon, Ron Sass. 1-6 [doi]
- Efficient reconfigurable hardware architecture for accurately computing success probability and data complexity of linear attacksAndrey Bogdanov, Elif Bilge Kavun, Elmar Tischhauser, Tolga Yalçin. 1-6 [doi]
- A scalable array for Cellular Genetic Algorithms: TSP as case studyPedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira. 1-6 [doi]
- Dreams: A tool for the design of dynamically reconfigurable embedded and modular systemsAndrés Otero, Eduardo de la Torre, Teresa Riesgo. 1-8 [doi]
- IPSecco: A lightweight and reconfigurable IPSec coreBenedikt Driessen, Tim Güneysu, Elif Bilge Kavun, Oliver Mischke, Christof Paar, Thomas Pöppelmann. 1-7 [doi]
- Isolation of behavior design from system implementationAndy Caley Data, Kent Gilson. 1-6 [doi]
- Akers's wavefront planner - One of the fastest stencil-based path planners on FPGAsMichael Schmidt, Dietmar Fey. 1-6 [doi]
- Developing application-specific multiprocessor platforms on FPGAsSen Ma, Miaoqing Huang, David L. Andrews. 1-6 [doi]
- Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devicesDawood Alnajiar, Masanori Hashimoto, Takao Onoye, Yukio Mitsuyama. 1-7 [doi]
- A versatile UDP/IP based PC ↔ FPGA communication platformNikolaos Alachiotis, Simon A. Berger, Alexandros Stamatakis. 1-6 [doi]
- Fault mitigation by means of dynamic partial reconfiguration of Virtex-5 FPGAsAndres Upegui, Julien Izui, Gilles Curchod. 1-6 [doi]
- Heterogeneous computer architectures: An image processing pipeline for optical metrologyMarc Reichenbach, Ralf Seidler, Dietmar Fey. 1-8 [doi]
- A low power configurable SoC for simulating delay-based audio effectsLing Liu, Jeremia Bar, Felix Friedrich, Jürg Gutknecht, Shiao Li Tsao. 1-6 [doi]
- Exploring hardware work queue support for lightweight threads in MPSoCsRahul R. Sharma, Yamuna Rajasekhar, Ron Sass. 1-6 [doi]
- A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systemsCuong Pham-Quoc, Zaid Al-Ars, Koen Bertels. 1-6 [doi]
- Power consumption model for partial and dynamic reconfigurationRobin Bonamy, Daniel Chillet, Sebastien Bilavarn, Olivier Sentieys. 1-8 [doi]
- Automatic generation of identical routing pairs for FPGA implemented DPL logicWei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo. 1-6 [doi]
- SPREX: A soft processor with Runahead executionKaveh Aasaraai, Andreas Moshovos. 1-7 [doi]
- Hardware design and implementation of a Network-on-Chip based load balancing switch fabricTurhan Karadeniz, Lotfi Mhamdi, Kees Goossens, J. J. Garcia-Luna-Aceves. 1-7 [doi]
- FPGA embedded single-cycle 16-bit microprocessor and toolsLuis Morales-Velazquez, Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso. 1-6 [doi]
- Parallelization of the estimation algorithm of the 3D structure tensorAshraful Alam, Zain-ul-Abdin, Bertil Svensson. 1-6 [doi]
- Pragma based parallelization - Trading hardware efficiency for ease of use?Tobias Kenter, Henning Schmitz, Christian Plessl. 1-8 [doi]
- Minimization of average execution time based on speculative FPGA configuration prefetchAdrian Alin Lifa, Petru Eles, Zebo Peng. 1-8 [doi]
- Compact trie forest: Scalable architecture for IP lookup on FPGAsOguzhan Erdem, Aydin Carus, Hoang Le. 1-6 [doi]
- A novel efficient FPGA architecture for HMMER accelerationMohd Nazrin Md. Isa, Khaled Benkrid, Thomas Clayton. 1-6 [doi]
- A High-Performance Reconfigurable Computing architecture using a magnetic configuration memoryVictor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto. 1-6 [doi]
- Resiliency-aware Scheduling for reconfigurable VLIW processorsJeremy Abramson, Pedro C. Diniz. 1-7 [doi]
- Two IP protection schemes for multi-FPGA systemsLubos Gaspar, Viktor Fischer, Tim Güneysu, Zouha Cherif Jouini. 1-6 [doi]
- An implementation of 3D Electron Tomography on FPGAsFrederik Griill, Michael Kunz, Michael Hausmann, Udo Kebschull. 1-5 [doi]
- Design of a multi-soft-core based Laser Marking controllerDavid Castells-Rufas, Oscar Vila-Closas, Jordi Carrabina. 1-6 [doi]
- Evaluating reconfigurable dataflow computing using the Himeno benchmarkYukinori Sato, Yasushi Inoguchi, Wayne Luk, Tadao Nakamura. 1-7 [doi]
- An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decodingVianney Lapotre, Guy Gogniat, Jean-Philippe Diguet, Salim Haddad, Amer Baghdadi. 1-6 [doi]
- A lightweight speculative and predicative scheme for hardware executionRazvan Nane, Vlad Mihai Sima, Koen Bertels. 1-6 [doi]
- Dynamic reconfiguration of modular I/O IP cores for avionic applicationsVenkatasubramanian Viswanathan, Benjamin Nakache, Rabie Ben Atitallah, Maurice Nakache, Jean-Luc Dekeyser. 1-6 [doi]
- A methodology for the design and deployment of reliable systems on heterogeneous platformsHugo A. Andrade, Arkadeb Ghosal, Kaushik Ravindran, Brian L. Evans. 1-7 [doi]
- Efficient parallel-pipelined GHASH for message authenticationKarim M. Abdellatif, Roselyne Chotin-Avot, Habib Mehrez. 1-6 [doi]
- A FPGA-based scalable architecture for URL legal filtering in 100GbE networksJaime J. Garnica, Sergio López-Buedo, Víctor López, Javier Aracil, José Maria Gómez Hidalgo. 1-6 [doi]
- Eight ways to put your FPGA on fire - A systematic study of heat generatorsMarkus Happe, Hendrik Hangmann, Andreas Agne, Christian Plessl. 1-6 [doi]
- Reducing the overall cache miss rate using different cache sizes for Heterogeneous Multi-core ProcessorsBruno de Abreu Silva, Lucas Albers Cuminato, Vanderlei Bonato. 1-6 [doi]
- Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGAUli Kretzschmar, Armando Astarloa, Jesús Lázaro, Mikel Garay, Javier Del Ser. 1-6 [doi]
- Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design FlowLaurent Gantel, Mohamed El Amine Benkhelifa, Fabrice Lemonnier, François Verdier. 1-6 [doi]
- FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN)Tobias Ziermann, Alexander Butiu, Jürgen Teich, Daniel Ziener. 1-6 [doi]
- Efficient and side-channel resistant authenticated encryption of FPGA bitstreamsAndrey Bogdanov, Amir Moradi, Tolga Yalçin. 1-6 [doi]
- FPGA-based rapid prototyping platform for MIMO-BICM design space explorationChristina Gimmler-Dumont, Philipp Schläfer, Norbert Wehn. 1-7 [doi]
- Optimizing the physical implementation of a reconfigurable cacheA. D. Santana Gil, M. Hernandez Calvino, F. J. Quiles Latorre, Ezequiel Herruzo Gomez, Jose Ignacio Benavides Benitez. 1-6 [doi]