Abstract is missing.
- Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI ModelHalil Kukner, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken. 1-7 [doi]
- Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement ChipVaradan Savulimedu Veeravalli, Thomas Polzer, Andreas Steininger, Ulrich Schmid. 8-17 [doi]
- Accurate Estimation of Leakage Power Variability in Sub-micrometer CMOS CircuitsOmid Assare, Mahmoud Momtazpour, Maziar Goudarzi. 18-25 [doi]
- reMORPH: A Runtime Reconfigurable ArchitectureKolin Paul, Chinmaya Dash, Mansureh Shahraki Moghaddam. 26-33 [doi]
- Designing a High Performance and Reliable Networks-on-Chip Using Network Interface Assisted Routing StrategyKhalid Latif 0002, Amir-Mohammad Rahmani, Tiberiu Seceleanu, Hannu Tenhunen. 34-41 [doi]
- A Scalable Monitoring Infrastructure for Self-Organizing Many-Core ArchitecturesDavid Kramer, Wolfgang Karl. 42-49 [doi]
- On the Design of Configurable Modulo 2n±1 Residue GeneratorsConstantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis, Kiamal Z. Pekmestzi. 50-56 [doi]
- Projected Don't CaresAnna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa. 57-64 [doi]
- SUT-RNS Residue-to-Binary Converters DesignEvangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos. 65-72 [doi]
- Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC CoresRoland Dobai, Marcel Baláz, Mária Fischerová. 73-78 [doi]
- Miscellaneous Types of Partial Duplication Modifications for Availability ImprovementsMartin Kohlík, Jaroslav Borecky, Hana Kubatova. 79-83 [doi]
- Reliability of Task Execution During Safe Software ProcessingPeter Raab, Stefan Kramer, Jürgen Mottok, Stanislav Racek. 84-89 [doi]
- Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron DomainDimitris Bekiaris, George Economakos. 90-97 [doi]
- OWQS: One-Way Quantum Computation SimulatorEesa Nikahd, Mahboobeh Houshmand, Morteza Saheb Zamani, Mehdi Sedighi. 98-104 [doi]
- The ACROSS MPSoC - A New Generation of Multi-core Processors Designed for Safety-Critical Embedded SystemsChristian El Salloum, Martin Elshuber, Oliver Höftberger, Haris Isakovic, Armin Wasicek. 105-113 [doi]
- From Scilab to High Performance Embedded Multicore Systems: The ALMA ApproachJürgen Becker, Timo Stripf, Oliver Oey, Michael Hübner, Steven Derrien, Daniel Menard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Göhringer. 114-121 [doi]
- FPGA Based Real-Time Tracking Approach with Validation of Precision and PerformanceAlexander Bochem, Kenneth B. Kent, Rainer Herpers. 122-127 [doi]
- Analyzing Bus Load Data Using an FPGA and a MicrocontrollerMarcel Dombrowski, Kenneth B. Kent, Yves G. Losier, Adam W. Wilson, Rainer Herpers. 128-131 [doi]
- On the Development of a Runtime Reconfigurable Multicore System-on-ChipAndrea Cazzaniga, Gianluca Durelli, Christian Pilato, Donatella Sciuto, Marco D. Santambrogio. 132-135 [doi]
- Resilient Adaptive Algebraic Architecture for Parallel Detection and Correction of Soft-ErrorsFábio P. Itturriet, Ronaldo Rodrigues Ferreira, Gustavo Girão, Gabriel L. Nazar, Álvaro F. Moreira, Luigi Carro. 136-139 [doi]
- Improving the Soft Error Resilience of the Register Files Using SRAM Bitcells with Built-In ComparatorsMehmet Kayaalp, Fahrettin Koc, Oguz Ergin. 140-143 [doi]
- Vulnerability Analysis for Custom InstructionsAli Azarpeyvand, Mostafa E. Salehi, Sied Mehdi Fakhraie. 144-147 [doi]
- A Three-Dimensional Integrated AcceleratorFarhad Mehdipour, Krishna Chaitanya Nunna, Koji Inoue, Kazuaki Murakami. 148-151 [doi]
- Algorithm Parallelism Estimation for Constraining Instruction-Set Synthesis for VLIW ProcessorsRoel Jordans, Rosilde Corvino, Lech Józwiak. 152-155 [doi]
- An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUFZouha Cherif, Jean-Luc Danger, Sylvain Guilley, Lilian Bossuet. 156-162 [doi]
- No Principal Too Small: Memory Access Control for Fine-Grained Protection DomainsEugen Leontie, Gedare Bloom, Bhagirath Narahari, Rahul Simha. 163-170 [doi]
- Hardware Strengthening a Distributed Logging SchemeJo Vliegen, Karel Wouters, Christian Grahn, Tobias Pulls. 171-176 [doi]
- Trojan Immune Circuits Using DualityYousra Alkabani. 177-184 [doi]
- Semi-distributed Control for FPGA-based Reconfigurable SystemsChiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser. 185-192 [doi]
- FPGA-based Neural Network for Nonuniformity Correction on Infrared Focal Plane ArraysNicolas Celedon, Rodolfo Redlich, Miguel Figueroa. 193-200 [doi]
- MAFA: Adaptive Fault-Tolerant Routing Algorithm for Networks-on-ChipMasoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila, Hannu Tenhunen. 201-207 [doi]
- Power and Thermal Analysis of Stacked Mesh 3D NoC Using AdaptiveXYZ Routing AlgorithmAmir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 208-215 [doi]
- ASAM: Automatic Architecture Synthesis and Application MappingLech Józwiak, Menno Lindwer, Rosilde Corvino, Paolo Meloni, Laura Micconi, Jan Madsen, Erkan Diken, Deepak Gangadharan, Roel Jordans, Sebastiano Pomata, Paul Pop, Giuseppe Tuveri, Luigi Raffo. 216-225 [doi]
- Controlling Hardware Synthesis with AspectsJoão M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk. 226-233 [doi]
- FASTER: Facilitating Analysis and Synthesis Technologies for Effective ReconfigurationDionisios N. Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Karel Bruneel, Georgi Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Oliver Pell, Christian Pilato, M. Robart, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman. 234-241 [doi]
- Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic ClassesSyed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen. 242-249 [doi]
- Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGAJan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek. 250-257 [doi]
- Activity Migration in M-of-N-Systems by Means of Load-BalancingMarkus Ulbricht, Heinrich Theodor Vierhaus, Tobias Koal. 258-263 [doi]
- Protecting an Asynchronous NoC against Transient Channel FaultsSyed Rameez Naqvi, Varadan Savulimedu Veeravalli, Andreas Steininger. 264-271 [doi]
- On Distribution and Impact of Fault Effects at Real-Time Kernel and Application LevelsJosef Strnadel, Frantiek Slimarik. 272-279 [doi]
- Exploiting Bus Level and Bit Level Inactivity for Preventing Wire Degradation due to ElectromigrationMehmet Kayaalp, Fahrettin Koc, Oguz Ergin. 280-287 [doi]
- A Heuristic Energy-Aware Approach for Hard Real-Time Systems on Multi-core PlatformsDa He, Wolfgang Mueller. 288-295 [doi]
- ONC3: All-Optical NoC Based on Cube-Connected Cycles with Quasi-DOR AlgorithmMeisam Abdollahi, Mohammad Khavari Tavana, Somayyeh Koohi, Shaahin Hessabi. 296-303 [doi]
- Architecture Support and Comparison of Three Memory Consistency Models in NoC Based SystemsAbdul Naeem, Axel Jantsch, Zhonghai Lu. 304-311 [doi]
- A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPsSandro Bartolini, Paolo Grani. 312-318 [doi]
- High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal ProcessingSheetal Bhandari, S. Subbaraman, S. Pujari, Fabio Cancare, Francesco Bruschi, Marco D. Santambrogio, Paolo Roberto Grassi. 319-326 [doi]
- The Seat Adaptation System of REFLECT Project: Implementation of a Biocybernetic Loop in an Automotive EnvironmentGian Mario Bertolotti, Andrea Cristiani, Remo Lombardi, Nikola B. Serbedzija. 327-334 [doi]
- The DeSyRe Project: On-Demand System ReliabilityIoannis Sourdis, Christos Strydis, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Alirad Malek, R. Mariani, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Kim Sunesen, Stavros Tzilis. 335-342 [doi]
- FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA KernelsIakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Mihai T. Lazarescu, Eduardo de la Torre, Florian Schäfer. 343-348 [doi]
- COMPLEX: COdesign and Power Management in PLatform-Based Design Space EXplorationKim Grüttner, Philipp A. Hartmann, Kai Hylla, Sven Rosinger, Wolfgang Nebel, Fernando Herrera, Eugenio Villar, Carlo Brandolese, William Fornaciari, Gianluca Palermo, Chantal Ykman-Couvreur, Davide Quaglia, Francisco Ferrero, Raúl Valencia. 349-358 [doi]
- Using Genetic Algorithm to Identify Soft-Error Derating Blocks of an Application ProgramBahman Arasteh, Amir Masoud Rahmani, Ali Mansoor, Seyed Ghassem Miremadi. 359-367 [doi]
- The Influence of Implementation Technology on Dependability ParametersJan Schmidt, Petr Fiser, Jiri Balcarek. 368-373 [doi]
- TSV-virtualization for Multi-protocol-Interconnect in 3D-ICsFelix Miller, Thomas Wild, Andreas Herkersdorf. 374-381 [doi]
- A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICsRadhika Jagtap, Sumeet S. Kumar, Rene van Leuken. 382-388 [doi]
- Multi-device Driver Synthesis Flow for Heterogeneous Hierarchical SystemsAlexandre Chagoya-Garzon, Frédéric Rousseau, Frédéric Pétrot. 389-396 [doi]
- A Verifiable High Level Data Path Synthesis FrameworkGorker Alp Malazgirt, Ender Culha, Alper Sen 0001, I. Faik Baskaya, Arda Yurdakul. 397-404 [doi]
- Finite State Machine Synthesis Based on Relay-Based AlgorithmM. Yang, Jinmei Lai, Hongying Xu. 405-410 [doi]
- VLSI Reverse Converter for RNS Based on the Moduli SetLeonel Sousa, Samuel Antao. 411-414 [doi]
- EJOP: An Extensible Java Processor with Reasonable Performance/Flexibility Trade-offSamaneh Talebi, Niloofar Abolghasemi, Ali Jahanian. 415-418 [doi]
- A Dual-Core Coprocessor with Native 4D Clifford Algebra SupportSilvia Franchini, Antonio Gentile, Giorgio Vassallo, Filippo Sorbello, Salvatore Vitabile. 419-422 [doi]
- SystemC Model Generation for Realistic Simulation of Networked Embedded SystemsMihai T. Lazarescu, Parinaz Sayyah, Davide Quaglia, Francesco Stefanni. 423-426 [doi]
- How to Prove that a Circuit is Fault-Free?Raimund Ubar, Sergei Kostin, Jaan Raik. 427-430 [doi]
- On Modeling and Evaluation of Logic Circuits under Timing VariationsMehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan. 431-436 [doi]
- IEEE 802.11p Receiver Design for Software Defined Radio PlatformsCarina Schmidt-Knorreck, Daniel Knorreck, Raymond Knopp. 437-444 [doi]
- Analytical Design Space Exploration Based on Statistically Refined Runtime and Logic Estimation for Software Defined RadiosMatthias Ihmig, Michael Feilen, Andreas Herkersdorf. 445-452 [doi]
- HDCRAM Proof-of-Concept for Opportunistic Spectrum AccessOussama Lazrak, Pierre Leray, Christophe Moy. 453-458 [doi]
- A Flexible Hardware Platform for Mobile Cognitive Radio ApplicationsVincent Berg, Dominique Noguet, Xavier Popon. 459-462 [doi]
- Flexible OFDM Waveform for PLC/RF In-Vehicle CommunicationsFabienne Nouvel, Philippe Tanguy. 463-468 [doi]
- Open Problems in Verification and Refinement of Autonomous Robotic SystemsDavide Bresolin, Luigi Di Guglielmo, Luca Geretti, Riccardo Muradore, Paolo Fiorini, Tiziano Villa. 469-476 [doi]
- Cyber-Physical Systems Design for Electric VehiclesMartin Lukasiewycz, Sebastian Steinhorst, Florian Sagstetter, Wanli Chang, Peter Waszecki, Matthias Kauer, Samarjit Chakraborty. 477-484 [doi]
- Simulation-Based Analysis of Cyberphysical SystemsMasahiro Fujita. 485-492 [doi]
- Model Checking on Hybrid AutomataAlberto Casagrande, Carla Piazza. 493-500 [doi]
- Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency ManagementRaphael Poss, Mike Lankamp, Qiang Yang 0006, Jian Fu, Michiel W. van Tol, Chris R. Jesshope. 501-508 [doi]
- HEAP: A Highly Efficient Adaptive Multi-processor FrameworkLuciano Lavagno, Mihai T. Lazarescu, Ioannis Papaefstathiou, Andreas Brokalakis, Johan Walters, Bart Kienhuis, Florian Schäfer. 509-516 [doi]
- System Adaptivity and Fault-Tolerance in NoC-based MPSoCs: The MADNESS Project ApproachPaolo Meloni, Giuseppe Tuveri, Luigi Raffo, Emanuele Cannella, Todor Stefanov, Onur Derin, Leandro Fiorin, Mariagiovanna Sami. 517-524 [doi]
- Coverage-Driven Stimuli GenerationShuo Yang, Robert Wille, Daniel Große, Rolf Drechsler. 525-528 [doi]
- Convolutional Decoding on Deep-pipelined SIMD Processor with Flexible Parallel MemoryJian Wang, Andreas Karlsson, Joar Sohl, Dake Liu. 529-532 [doi]
- Hardware Acceleration of STON Algorithm for Comparing 3-D Structure of ProteinsSomayeh Kashi, Morteza Saheb Zamani. 533-536 [doi]
- High Level Modeling and Simulation of a Baseband Processor for the 60 GHz BandRuben Cabral, Helena Sarmento. 537-540 [doi]
- A Virtual Platform for Performance Estimation of Many-core ImplementationsPablo González de Aledo Marugán, Javier Gonzalez Bayon, Pablo Sánchez Espeso. 541-544 [doi]
- Differential Scan Attack on AES with X-tolerant and X-masked Test Response CompactorBaris Ege, Amitabh Das, Santosh Ghosh, Ingrid Verbauwhede. 545-552 [doi]
- A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA PlatformsSujoy Sinha Roy, Chester Rebeiro, Debdeep Mukhopadhyay. 553-559 [doi]
- Evaluating Cryptanalytical Strength of Lightweight Cipher PRESENT on Reconfigurable HardwareJan Pospísil, Martin Novotný. 560-567 [doi]
- A High-Speed Unified Hardware Architecture for AES and the SHA-3 Candidate GrøstlMarcin Rogawski, Kris Gaj. 568-575 [doi]
- Minimizing Power Consumption of Spatial Division Based Networks-on-Chip Using Multi-path and Frequency ReductionSheng Hao Wang, Anup Das, Akash Kumar, Henk Corporaal. 576-583 [doi]
- Optimal 2D Data Partitioning for DMA Transfers on MPSoCsSelma Saidi, Pranav Tendulkar, Thierry Lepley, Oded Maler. 584-591 [doi]
- Distance-Constrained Force-Directed Process Mapping for MPSoC ArchitecturesTimo Schönwald, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel. 592-599 [doi]
- Reducing Instruction Issue Overheads in Application-Specific Vector ProcessorsJaroslav Sykora, Roman Bartosinski, Lukas Kohout, Martin Danek, Petr Honzík. 600-607 [doi]
- Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC PlatformsPrashant Agrawal, Kanishk Sugand, Martin Palkovic, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor. 608-615 [doi]
- Adaptive Field Strength ScalingL: A Power Optimization Technique for Contactless Reader / Smart Card SystemsNorbert Druml, Manuel Menghin, Christian Steger, Reinhold Weiss, Andreas Genser, Holger Bock, Josef Haid. 616-623 [doi]
- RF-Interconnect Resource Assignment and Placement Algorithms in Application Specific ICs to Improve Performance and Reduce Routing CongestionBahareh Pourshirazi, Ali Jahanian. 624-631 [doi]
- High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVCTiago Dias, Luis Rosario, Nuno Roma, Leonel Sousa. 632-639 [doi]
- JAAVR: Introducing the Next Generation of Security-Enabled RFID TagsErich Wenger, Thomas Baier 0002, Johannes Feichtner. 640-647 [doi]
- FPGA-based Design Approaches of Keccak Hash FunctionGeorge Provelengios, Paris Kitsos, Nicolas Sklavos, Christos Koulamas. 648-653 [doi]
- PROCOMON: An Automatically Generated Predictive Control Signal MonitorArmin Krieg, Johannes Grinschgl, Norbert Druml, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 654-660 [doi]
- CRT RSA Hardware Architecture with Fault and Simple Power Attack CountermeasuresApostolos P. Fournaris, Odysseas G. Koufopavlou. 661-667 [doi]
- Open-People: Open Power and Energy Optimization PLatform and EstimatorEric Senn, Daniel Chillet, Olivier Zendra, Cécile Belleudy, Sebastien Bilavarn, Rabie Ben Atitallah, Christian Samoyeau, A. Fritsch. 668-675 [doi]
- A Hardware-In-the-Design Methodology for Wireless Sensor Networks Based on Event-Driven Impulse Radio Ultra-Wide BandAlberto Bonanno, Alessandro Sanginario, Marco Crepaldi, Danilo Demarchi. 676-683 [doi]
- Energy Characterization and Classification of Embedded Operating System ServicesBassem Ouni, Cécile Belleudy, Eric Senn. 684-691 [doi]
- Enhanced IP-XACT Platform Descriptions for Automatic Generation from UML/MARTE of Fast Performance Models for DSEFernando Herrera, Hector Posadas, Eugenio Villar, Daniel Calvo. 692-699 [doi]
- Automated Generation of Embedded Systems Software from Timed DEVS Model of Computation SpecificationsH. Gregor Molter, Johannes Kohlmann, Sorin A. Huss. 700-707 [doi]
- Generation of VHDL Code from UML/MARTE Sequence Diagrams for Verification and SynthesisEmad Samuel Malki Ebeid, Davide Quaglia, Franco Fummi. 708-714 [doi]
- Extending MARTE to Support the Specification and the Generation of Data Intensive Applications for Massively Parallel SoCManel Ammar, Mouna Baklouti, Mohamed Abid. 715-722 [doi]
- Managing a Massively-Parallel Resource-Constrained Computing ArchitectureCameron Patterson, Thomas Preston, Francesco Galluppi, Steve Furber. 723-726 [doi]
- Evaluation of a Connectionless NoC for a Real-Time Distributed Shared Memory Many-Core SystemJochem H. Rutgers, Marco Jan Gerrit Bekooij, Gerard J. M. Smit. 727-730 [doi]
- CoolMap: A Thermal-Aware Mapping Algorithm for Application Specific Networks-on-ChipMostafa Moazzen, Akram Reza, Midia Reshadi. 731-734 [doi]
- Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic CircuitHiroki Ito, Mitsuru Shiozaki, Anh Tuan Hoang, Takeshi Fujino. 735-738 [doi]
- A Distributed Feedback Control Mechanism for Quality-of-Service Maintenance in Wireless Sensor NetworksMarcel Steine, Marc Geilen, Twan Basten. 739-742 [doi]
- MAMOT: Memory-Aware Mapping Optimization Tool for MPSoCOlivera Jovanovic, Peter Marwedel, Iuliana Bacivarov, Lothar Thiele. 743-750 [doi]
- OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory ClustersPaolo Burgio, Andrea Marongiu, Dominique Heller, Cyrille Chavet, Philippe Coussy, Luca Benini. 751-758 [doi]
- A Game Theoretical Thermal - Aware Run - Time Task Synchronization Method for Multiprocessor Systems - on - ChipYashar Asgarieh, Mohammad-Hassan Khabbazian, Mehdi Modarressi, Hamid Sarbazi-Azad. 759-765 [doi]
- Composable Virtual Memory for an Embedded SoCCor Meenderinck, Anca Mariana Molnos, Kees Goossens. 766-773 [doi]
- Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case StudyRosilde Corvino, Erkan Diken, Abdoulaye Gamatié, Lech Józwiak. 774-781 [doi]
- Parallel Decimal Multipliers and Squarers Using Karatsuba-Ofman's AlgorithmMário P. Véstias, Horácio C. Neto. 782-788 [doi]
- The Synthesis of Combined Mealy and Moore Machines Structural Model Using Values of Output Variables as Codes of StatesAdam Klimowicz, Valery Salauyou. 789-794 [doi]
- RNS Arithmetic Units for Modulo {2^n+-k}Pedro Miguens Matutino, Héctor Pettenghi, Ricardo Chaves, Leonel Sousa. 795-802 [doi]
- Scalability Study of Polymorphic Register FilesCatalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev. 803-808 [doi]
- Pipelined Large Multiplier Designs on FPGAsAli Sentürk, Mustafa Gök. 809-814 [doi]
- Implementation Study of FFT on Multi-lane Vector ProcessorsBogdan Spinean, Georgi Gaydadjiev. 815-822 [doi]
- Robust Evaluation of Weighted Random Logic BIST Structures in Industrial DesignsRene Krenz-Baath, Friedrich Hapke, Rolf Hinze, Reinhard Meier, Maija Ryynaenen, Andreas Glowatz. 823-829 [doi]
- Test Generation Approach for Post-Silicon Validation of High End MicroprocessorSatish Kumar Sadasivam, Sangram Alapati, Varun Mallikarjunan. 830-836 [doi]
- Investigating Dependability of Short-Range Wireless Embedded Systems through Hardware Platform Based DesignBenaoumeur Senouci, Anne-Johan Annema, Mark J. Bentum, Hans G. Kerkhoff. 837-843 [doi]
- Scan Based Tests via Standard InterfacesChristian Gleichner, Heinrich Theodor Vierhaus, Piet Engelke. 844-851 [doi]
- Soft Error Analysis on Communication Channels in On-Chip Communication NetworksMohammadreza Najafi, Saeed Safari, Zainalabedin Navabi. 852-857 [doi]
- Virtual Platform for Wireless Sensor NetworksAlvaro Diaz Suarez, Raul Diego, Pablo Sanchez. 858-865 [doi]
- Energy-Aware FPGA-based Architecture for Wireless Sensor NetworksPaolo Roberto Grassi, Donatella Sciuto. 866-873 [doi]
- Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor NetworksPaolo Roberto Grassi, Vincenzo Rana, Ivan Beretta, Donatella Sciuto. 874-881 [doi]
- A Predictor-Based Power-Saving Policy for DRAM MemoriesGervin Thomas, Karthik Chandrasekar 0001, Benny Akesson, Ben H. H. Juurlink, Kees Goossens. 882-889 [doi]
- Evaluation of an FPGA-based Reconfigurable SoC for All-Digital Flexible RF TransmittersNelson V. Silva, Manuel Ventura, Arnaldo S. R. Oliveira, Nuno Borges Carvalho. 890-895 [doi]
- Design and Implementation of a Circuit for Mesh Networks with Application in Body Area NetworksFardin Derogarian, João Canas Ferreira, Vitor M. Grade Tavares. 896-901 [doi]
- H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore ProcessorsElias Baaklini, Hassan Sbeity, Smaïl Niar. 902-906 [doi]
- Enhanced Omnidirectional Image Reconstruction Algorithm and Its Real-Time HardwareAbdulkadir Akin, Elif Erdede, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici. 907-914 [doi]
- A Small and High-Performance Coprocessor for Fingerprint Match-on-CardTaoufik Chouta, Jean-Luc Danger, Laurent Sauvage, Tarik Graba. 915-922 [doi]
- On-Package Scalability of RF and Inductive Memory ControllersMario Donato Marino. 923-930 [doi]
- A Hardware Accelerator for Real Time Simulation of Complex Neuronal ModelsAlessandra Majani, Maria Chiara Lorena, Giovanni Danese, Francesco Leporati. 931-937 [doi]
- Design of High-Speed Viterbi Decoders on Virtex-6 FPGAsMário P. Véstias, Horácio C. Neto, Helena Sarmento. 938-945 [doi]