Abstract is missing.
- Keynote speachNikil Dutt. [doi]
- Hardware-assisted virtualization targeting MIPS-based SoCsAlexandra Aguiar, Carlos Moratelli, Marcos Sartori, Fabiano Hessel. 2-8 [doi]
- Buffer depth and traffic influence on 3D NoCs performanceYan Ghidini, Thais Webber, Edson I. Moreno, Fernando Grando, Rubem Dutra Ribeiro Fagundes, César A. M. Marcon. 9-15 [doi]
- A model-based I/O interface synthesis framework for the cross-platform software modelingBaekGyu Kim, Linh T. X. Phan, Insup Lee, Oleg Sokolsky. 16-22 [doi]
- Case study: Deployment of the 2D NoC on 3D for the generation of large emulation platformsVirginie Fresse, Zhiwei Ge, Junyan Tan, Frédéric Rousseau. 23-29 [doi]
- A spectrum of MPSoC models for design space exploration and its useCarlos A. Petry, Eduardo Wächter, Guilherme M. Castilhos, Fernando Gehm Moraes, Ney Laert Vilar Calazans. 30-35 [doi]
- Graphically notated fault modeling and safety analysis in the context of electric and electronic architecture development and functional safetyNico Adler, Martin Hillenbrand, Klaus D. Müller-Glaser, Eduard Metzker, Clemens Reichmann. 36-42 [doi]
- Parity-based mono-Copy Cache for low power consumption and high reliabilityIhsen Alouani, Smaïl Niar, Fadi J. Kurdahi, Mohamed Abid. 44-48 [doi]
- A cycle-level parallel simulation technique exploiting both space and time parallelismDukyoung Yun, Youngmin Yi, Sungchan Kim, Soonhoi Ha. 50-56 [doi]
- An ArchC approach for automatic energy consumption characterization of processorsMarcelo Guedes, Rafael Auler, Edson Borin, Rodolfo Azevedo. 57-63 [doi]
- Automatic congestion detection in MPSoC programs using data mining on simulation tracesSofiane Lagraa, Alexandre Termier, Frédéric Pétrot. 64-70 [doi]
- Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA boardQingshan Tang, Habib Mehrez, Matthieu Tuna. 71-77 [doi]
- HySon: Set-based simulation of hybrid systemsOlivier Bouissou, Samuel Mimram, Alexandre Chapoutot. 79-85 [doi]
- Automatic generation of observers from MARTE/CCSLFrédéric Mallet. 86-92 [doi]
- Integrating semantic properties within a Petri net based scheduling toolChristian Fotsing, Annie Geniet. 93-99 [doi]
- Seamless model-based design and deployment of wireless networked systemsTobias Schwalb, Tobias Gädeke, Johannes Schmid, Klaus D. Müller-Glaser. 100-106 [doi]
- Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACTGilberto Ochoa-Ruiz, Ouassila Labbani, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser. 107-113 [doi]
- Challenges in software development for multicore System-on-Chip developmentIan Gray, Neil C. Audsley. 115-121 [doi]
- A new approach for pin detection for an electronic system prototyping reconfigurable platformHai H. Nguyen, Mikael Guillemot, Yvon Savaria, Yves Blaquière. 122-127 [doi]
- Visualization support for FPGA architecture explorationKonstantin Nasartschuk, Rainer Herpers, Kenneth B. Kent. 128-134 [doi]
- Integrated architecture exploration workflow: A NoC-based case studyDiego Puschini, Julien Mottin, Nicolas Palix, Lian Apostol, Christian Fabre. 135-141 [doi]
- FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and DecodingPurushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi, Michel Jézéquel. 143-148 [doi]
- Fault-aware task re-mapping for throughput constrained multimedia applications on NoC-based MPSoCsAnup Das, Akash Kumar. 149-155 [doi]
- System-level prototyping framework for heterogeneous multi-core architecture applied to biological sequence analysisNuno Roma, Pedro Magalhães. 156-162 [doi]
- FlashBench: A workbench for a rapid development of flash-based storage devicesSungjin Lee, Jisung Park, Jihong Kim. 163-169 [doi]
- A design flow for partially reconfigurable heterogeneous multi-processor platformsLi Jiashu, Anup Das, Akash Kumar. 170-176 [doi]
- Reducing communication costs on Dynamic Networks-on-Chip through runtime relocation of tasksPhilipp Mahr, Christophe Bobda. 177-182 [doi]