Abstract is missing.
- Application Scenarios in Streaming-Oriented Embedded System DesignStefan Valentin Gheorghita, Twan Basten, Henk Corporaal. 1-4 [doi]
- Enhanced legacy 68000 instruction set architecture as a basis for system on chip developmentWojciech Sakowski, Wlodzimierz Wrona, Sebastian Kaprowski, Maciej Przybysz. 1-4 [doi]
- The Impact of Communication on the Scalability of the Data-parallel Video Encoder on MPSoCErno Salminen, Tero Kangas, Timo Hämäläinen 0001. 1-4 [doi]
- System Level Design Experiences and the Need for StandardizationVesa Lahtinen. 1-4 [doi]
- Efficient Link Architecture for On-Chip Serial links and NetworksJ. Balachandran, Maarten Kuijk, Steven Brebels, Geert Carchon, Walter De Raedt, Bart Nauwelaers, Eric Beyne. 1-4 [doi]
- Register File Partitioning with Constraint ProgrammingPerttu Salmela, Chung-Ching Shen, Shuvra S. Bhattacharyya, Jarmo Takala. 1-4 [doi]
- Hardware Cost Analysis for Weakly Programmable Processor ArraysDmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich. 1-4 [doi]
- Algorithms for Leakage Reduction with Dual Threshold Design TechniquesKonrad Engel, Thomas Kalinowski, Roger Labahn, Frank Sill, Dirk Timmermann. 1-4 [doi]
- High-Level Optimization of Asynchronous Systems Utilizing Conditional RestructuringMahtab Niknahad, Kamran Saleh, Mehrdad Najibi, Hossein Pedram. 1-6 [doi]
- Evaluation of current QoS Mechanisms in Networks on ChipAline Mello, Leonel Tedesco, Ney Calazans, Fernando Moraes 0001. 1-4 [doi]
- Implementation of an HSDPA Receiver with a Customized Vector ProcessorKim Rounioja, Kimmo Puusaari. 1-4 [doi]
- Parameterizing Simulated Annealing for Distributing Task Graphs on Multiprocessor SoCsHeikki Orsila, Tero Kangas, Erno Salminen, Timo Hämäläinen 0001. 1-4 [doi]
- An Ultra Low-Power Body Sensor Network Control Processor with Centralized Node ControlSungdae Choi, Kyomin Sohn, Hyejung Kim, Joo-Young Kim 0001, Seong-Jun Song, Namjun Cho, Jerald Yoo, Hoi-Jun Yoo. 1-4 [doi]
- Loop Scheduling for Transport Triggered Architecture ProcessorsPerttu Salmela, Risto Mäkinen, Pekka Jääskeläinen, Jarmo Takala. 1-4 [doi]
- Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time ManagementChantal Ykman-Couvreur, Vincent Nollet, Francky Catthoor, Henk Corporaal. 1-4 [doi]
- Development and Verification of Embedded Firmware using Virtual System PrototypesThomas Eckart, Martin Schnieringer. 1 [doi]
- IP Reuse for Flexible & Efficient DSP Platform ChipsPaul M. Heysters. 1 [doi]
- Programmability in Dictionary-Based CompressionJari Heikkinen, Jarmo Takala. 1-4 [doi]
- Dataflow Transformations in High-level DSP System DesignSankalita Saha, Sebastian Puthenpurayil, Shuvra S. Bhattacharyya. 1-6 [doi]
- External Memory Controller for Virtex II ProBlagomir Donchev, Georgi Kuzmanov, Georgi Nedeltchev Gaydadjiev. 1-4 [doi]
- Exploring Application-Level Concurrency in SoC DesignLeandro Soares Indrusiak. 1-4 [doi]
- Design And Verification of a VHDL Model of a Floating-Point Unit for a RISC MicroprocessorClaudio Brunelli, Jari Nurmi. 1-4 [doi]
- Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA ResourcesGabriel Caffarena, Juan A. López, Carlos Carreras, Octavio Nieto-Taladriz. 1-4 [doi]
- Fault-tolerant Routing Approach for Reconfigurable Networks-on-ChipPekka Rantala, Teijo Lehtonen, Jouni Isoaho, Juha Plosila. 1-4 [doi]
- Analog Television, WiMAX and DVB-H on the Same SoC PlatformDaniel Iancu, Hua Ye 0003, Vladimir Kotlyar, Murugappan Senthilvelan, John Glossner, Gary Nacer, Andrei Iancu, Jarmo Takala. 1-4 [doi]
- A Validation And Performance Evaluation Tool for ProtoNoCDavid Castells-Rufas, Jaume Joven, Jordi Carrabina. 1-4 [doi]
- SIxD: A Configurable Application-Specific SISD/SIMD Microprocessor Soft-CoreNehir Sönmez, Arda Yurdakul. 1-4 [doi]
- A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCsMartino Ruggiero, Pari Gioia, Guerri Alessio, Luca Benini, Michela Milano, Davide Bertozzi, Alexandru Andrei. 1-4 [doi]
- Using Constraint Programming to Achieve Optimal Prefetch Scheduling for Dependent Tasks on Run-Time Reconfigurable DevicesYang Qu, Juha-Pekka Soininen, Jari Nurmi. 1-4 [doi]
- Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on ChipsSrinivasan Murali, Rutuparna Tamhankar, Federico Angiolini, Antonio Pullini, David Atienza, Luca Benini, Giovanni De Micheli. 1-4 [doi]
- Minimising Dynamic Power Consumption in On-Chip NetworksRobert Mullins. 1-4 [doi]
- Reconfigurable Fabric InterconnectsStamatis Vassiliadis, Ioannis Sourdis. 1-4 [doi]
- Non-Power-of-Two FFTs: Exploring the Flexibility of the MONTIUMPascal T. Wolkotte, Marcel D. van de Burgwal, Gerard J. M. Smit. 1-4 [doi]
- Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suiteGert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet. 1-4 [doi]
- Formal Modelling of Multiclocked SoC SystemsTomi Westerlund, Juha Plosila. 1-4 [doi]
- Power Estimation for IP-Based ModulesYaseer Arafat Durrani, Teresa Riesgo. 1-4 [doi]
- Structural Verification in Minimal TimeMartin Holzer 0002, Bastian Knerr, Markus Rupp. 1-4 [doi]
- The Future of Nanometer SOC DesignSteve Leibson. 1-6 [doi]
- Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal OverheadFabrizio Ferrandi, Marco Novati, Massimo Morandi, Marco D. Santambrogio, Donatella Sciuto. 1-4 [doi]
- Using SPIRIT Cores in SonicsStudioKamil Synek. 1-4 [doi]
- Modeling And Performance Analysis of GALS architecturesSohini Dasgupta, Alex Yakovlev. 1-4 [doi]
- Serial Bus Encoding for Low Power ApplicationMohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi. 1-4 [doi]
- Multilevel MPSoC Performance Evaluation Using MDE ApproachRabie Ben Atitallah, Lossan Bonde, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser. 1-4 [doi]
- Minimizing Hot Spots in NoCs through a Dynamic Routing Algorithm based on Input and Output SelectionsMasoud Daneshtalab, Ali Afzali-Kusha, Siamak Mohammadi. 1-4 [doi]
- Analysis of Crosstalk and Process Variations Effects on On-Chip InterconnectsEthiopia Nigussie, Sampo Tuuna, Juha Plosila, Jouni Isoaho. 1-4 [doi]
- A High-Throughput Network-on-Chip Architecture for Systems-on-Chip InterconnectAbdelhafid Bouhraoua, Muhammad E. S. Elrabaa. 1-4 [doi]
- Realizing Multioperations for Step Cached MP-SOCsMartti Forsell. 1-6 [doi]
- Interconnection Generation for System-on-Chip DesignMarkus Winter 0002, Gerhard P. Fettweis. 1-4 [doi]
- A Leak Resistant SoC to Counteract Side Channel AttacksDaniel Mesquita, Benoît Badrignans, Lionel Torres, Gilles Sassatelli, Michel Robert, Fernando Gehm Moraes. 1-4 [doi]