Abstract is missing.
- A scalable and flexible data synchronization scheme for embedded HW-SW shared-memory systemsOm Prakash Gangwal, André Nieuwland, Paul E. R. Lippens. 1-6
- Exploiting scratch-pad memory using Presburger formulasMahmut T. Kandemir, Ismail Kadayif, Ugur Sezer. 7-12
- An optimal memory allocation for application-specific multiprocessor system-on-chipSamy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya. 19-24
- APEXPeter Grun, Nikil D. Dutt, Alexandru Nicolau. 25-32
- Powering networks on chipsLuca Benini, Giovanni De Micheli. 33-38
- Retargetable static timing analysis for embedded softwareKaiyu Chen, Sharad Malik, David I. August. 39-44
- On-line fault detection in a hardware/software co-design environmentCristiana Bolchini, Luigi Pomante, Fabio Salice, Donatella Sciuto. 51-56
- Using static scheduling techniques for the retargeting of high speed, compiled simulators for embedded processors from an abstract machine descriptionGunnar Braun, Andreas Hoffmann, Achim Nohl, Heinrich Meyr. 57-62
- Design and simulation of a pipelined decompression architecture for embedded systemsHaris Lekatsas, Jörg Henkel, Wayne Wolf. 63-68
- RTL semantics and methodologyBrian Bailey, Daniel Gajski. 69-74
- SystemCPreeti Ranjan Panda. 75-80
- The standard SpecC languageMasahiro Fujita, Hiroshi Nakamura. 81-86
- Interoperability as a design issue in C++ based modeling environmentsFrederic Doucet, Rajesh K. Gupta, Masato Otsuka, Patrick Schaumont, Sandeep K. Shukla. 87-92
- Bridging the gap between ISA compilers and silicon compilers a challenge for future SoC designGuang R. Gao. 93
- New design paradigmsWolfgang Rosenstiel, Brian Bailey, Masahiro Fujita, Guang R. Gao, Rajesh K. Gupta, Preeti Ranjan Panda. 94
- Loop fusion for memory space optimizationAntoine Fraboulet, Karen Kodary, Anne Mignotte. 95-100
- Cache-efficient memory layout of aggregate data structuresPreeti Ranjan Panda, Luc Séméria, Giovanni De Micheli. 101-106
- Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applicationsMiguel Miranda, C. Ghez, Chidamber Kulkarni, Francky Catthoor, Diederik Verkest. 107-112
- Data cache energy minimizations through programmable tag size matching to the applicationsPeter Petrov, Alex Orailoglu. 113-117
- Phase coupled operation assignment for VLIW processors with distributed register filesMarco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen. 118-123
- An energy efficient rate selection algorithm for voltage quantized dynamic voltage scalingLama H. Chandrasena, Priyadarshana Chandrasena, Michael J. Liebelt. 124-129
- Current consumption dynamics at instruction and program level for a ::::VLIW:::: DSP processorRadu Muresan, Catherine H. Gebotys. 130-135
- Dynamic modeling of inter-instruction effects for execution time estimationGiovanni Beltrame, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto, Vito Trianni. 136-141
- System level optimization and design space exploration for low powerAnsgar Stammermann, Lars Kruse, Wolfgang Nebel, Alexander Pratsch, Eike Schmidt, Milan Schulte, Arne Schulz. 142-146
- Efficient instruction-level optimization methodology for low-power embedded systemsKyu-won Choi, Abhijit Chatterjee. 147-152
- Source code transformation based on software cost analysisEui-Young Chung, Luca Benini, Giovanni De Micheli. 153-158
- Static resource models of instruction setsQin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess. 159-164
- Combined instruction and loop parallelism in array synthesis for FPGAsSteven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay. 165-170
- Conditional speculation and its effects on performance and area for high-level snthesisSumit Gupta, Nick Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. 171-176
- A data scheduler for multi-context reconfigurable architecturesMarcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh. 177-182
- Scheduling and partitioning for multiple loop nestsZhong Wang, Qingfeng Zhuge, Edwin Hsing-Mean Sha. 183-188
- Object oriented hardware synthesis and verificationTommy Kuhn, Tobias Oppold, C. Schulz-Key, Markus Winterholer, Wolfgang Rosenstiel, Mark Edwards, Yaron Kashai. 189-194
- System design of a telecommunication routerRichard Norman. 196
- Network processing in content inspection applicationsFeliks J. Welfeld. 197-201
- Programming models for network processors (Panel)Ahmed Amine Jerraya, Pierre G. Paulin, Richard Norman, Feliks J. Welfeld. 202
- Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faultsChien-In Henry Chen. 203-208
- Methods for optimizing register placement in synchronous circuits derived using software pipelining techniquesNoureddine Chabini, Yvon Savaria. 209-214
- High-level automatic pipelining for sequential circuitsMaria-Cristina V. Marinescu, Martin C. Rinard. 215-220
- Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing enginesJoonseok Park, Pedro C. Diniz. 221-226
- Soft-cores generation by instruction set analysisAlessandro Fin, Franco Fummi, Giovanni Perbellini. 227-232
- Concurrent-simulation-based remote IP evaluation over the internet for system-on-a-chip designHung-Pin Wen, Chien-Yu Lin, Youn-Long Lin. 233-238
- Application of Software design patterns to DSP library designPontus Åström, Stefan Johansson, Peter Nilsson. 239-243
- Accelerating boolean satisfiability through application specific processingYing Zhao, Sharad Malik, Matthew W. Moskewicz, Conor F. Madigan. 244-249
- Considering power variations of DVS processing elements for energy minimisation in distributed systemsMarcus T. Schmitz, Bashir M. Al-Hashimi. 250-255
- Functional abstraction driven design space exploration of heterogeneous programmable architecturesPrabhat Mishra, Nikil D. Dutt, Alexandru Nicolau. 256-261
- Modeling and simulation of steady state and transient behaviors for emergent SoCsJoAnn M. Paul, Arne J. Suppé, Donald E. Thomas. 262-267
- Synthesizing distributed real-time systems modeled by a timed version of a subset of LOTOSAhmed Khoumsi. 268-273
- Control and communication performance analysis of embedded DSP systems in the MASIC methodologyAbhijit K. Deb, Johnny Öberg, Axel Jantsch. 274-273